Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization

Assignee: International Business Machines Corp

•

Filing: 1992-04-10

•

Granted: —

•

Expires: 2012-04-10

📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of providing sublayer contacts in vertical walled trenches is proposed. In accordance with the present invention, the phosphorus doped amorphous silicon is deposited at temperatures less than 570°C. The conversion into the extremely large crystal low resistivity polysilicon is accomplished by a low temperature anneal at 400°C to 500°C for several hours and the short RTA treatment at a high temperature approximately 850°C for twenty seconds. These two conversion heat treatments are done at sufficiently thermal budget to prevent any significant dopant movement within a shallow junction transistor. After anneal, the excess low resistivity silicon is planarized away by known techniques such as chemical/mechanical polishing. In addition, due to the trench filling abilities of the amorphous silicon CVD process, in one preferred embodiment of the invention the capability of accessing subsurface silicon layers at different trench depths is demonstrated.

Inventors

👤 Edward C. Fredericks
👤 Louis L. Hsu
👤 David E. Kotecki
👤 Christopher C. Parks

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-09 22:29

CPC Classifications

H; H10; H10P; H10P14/00; H10P14/20; H10P14/38; H10P14/3802; H10P14/24; H10P14/29; H10P14/2924; H10P14/2925; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3438; H10P14/3441; H10P14/3442; H10P14/3444; H10P14/36; H10W; H10W20/00; H10W20/01; H10W20/021; Y; Y10; Y10S; Y10S148/00; Y10S148/05

Claims Analysis

Total Claims: 8

Claim 1

Independent Claim 136 words

A method of filling at least one trench (17, 19) in a surface of a semiconductor substrate comprising the steps of: providing a surface of said semiconductor substrate having at least one trench having substantially vertical sidewalls extending down from said surface to a sublayer of said semiconductor substrate to a chemical vapor deposition system; evacuating and heating said chemical vapor deposition system to a temperature less than 570°C; entering a mixture of silicon containing source gas and a dopant source gas into said chemical vapor deposition system to form a layer (29) of doped amorphous silicon; annealing said layer (29) of doped amorphous silicon at a temperature less than 500°C to form a doped nearly single crystalline silicon layer; and, activating a dopant in said doped amorphous silicon layer through a short, high temperature anneal.

Claim 2

Dependent Claim 22 words

The method as recited in claim 1 wherein said dopant source gas is selected from the group of PH₃, AsH₃ and B₂H₆.

Claim 3

Independent Claim 113 words

A method of forming a plurality of sublayer contacts in a surface of a semiconductor substrate having a plurality of vertically-walled trenches etched therein and extending to at least one sublayer of said semiconductor substrate comprising the steps of: depositing a layer of doped amorphous silicon on said surface in a chemical vapor deposition system at a temperature less than 570°C from a mixture of a silicon containing source gas and a dopant source gas; annealing said layer of doped amorphous silicon at a temperature less than 500°C to form a doped nearly single crystalline silicon layer; and, activating a dopant in said doped amorphous silicon layer through a short, high temperature anneal.

Claim 4

Independent Claim 31 words

The method as recited in anyone of the preceding claims which further comprises the step of removing the excess portions of said nearly single crystalline silicon layer through a planarization process.

Claim 5

Independent Claim 24 words

The method as recited in anyone of the preceding claims wherein said doped, nearly single crystalline silicon in said trench forms a sublayer contact.

Claim 6

Independent Claim 60 words

The method as recited in anyone of the preceding claims wherein said semiconductor substrate surface has a plurality of trenches at least one of which extends downward to a different sublayer of said semiconductor substrate than a second of said plurality of trenches, and said doped, nearly single crystalline silicon in said trenches form a plurality of different sublayer contacts.

Claim 7

Dependent Claim 15 words

The method as recited in claim 6 wherein at least one subcollector contact is formed.

Claim 8

Independent Claim 30 words

The method as recited in anyone of the preceding claims which further comprises the step of densifying said doped amorphous silicon at an elevated temperature immediately after said entering step.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag

Select Category

Notes (Optional)