Patent US4431555A successfully refreshed from Google Patents.
Patent EP0514679A2 successfully refreshed from Google Patents.
EP0514679A2
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EP
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Semiconductor integrated memory device
Assignee: Hitachi Ltd
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Filing: 1992-04-23
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Granted: —
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Expires: 2012-04-23
Abstract
Abstract A semiconductor integrated circuit device has a semiconductor memory cell array. The cell array includes word lines and data lines and a plurality of memory cells each provided at a cross point between one of the word lines and one of the data lines. Each memory cell has a cell selection transistor and an information storage capacitor connected in series. The cell selection transistor in one cell includes first and second doped regions (SR) formed in a main surface of a semiconductor substrate, a first insulating film (35) formed on the main surface of the semiconductor substrate between the first and second doped regions and a control electrode layer (36) formed on the first insulating film between the first and second doped regions. The first doped region is connected with a data line (55), while the control electrode is connected with a word line (36). The information storage capacitor includes a second insulating film (29) formed on the wall of one trench formed on the main surface of the semiconductor substrate, an electrode layer (30) formed on the second insulating film and serving as a first electrode of the capacitor, a dielectric film (32) formed on the electrode layer and a conducting material (33) provided to fill a space defined by the dielectric film in the trench and serving as a second electrode of the capacitor. The second doped region of the transistor terminates at the wall of the trench. A conducting layer (42) is provided to extend both on the second doped region and the conducting material in the cell to electrically interconnect them for the series connection.
Inventors
- 👤 Yoshitaka Tadaki
- 👤 Toshihiro Sekiguchi
- 👤 Hiroyuki Uchiyama
- 👤 Toru Kaga
- 👤 Jun Murata
- 👤 Osaomi Enomoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 14:26
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0385; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
310 words
A semiconductor integrated circuit device having a semiconductor memory cell array, said cell array including word lines and data lines and a plurality of memory cells each provided at a cross point between one of said word lines and one of said data lines and having a cell selection transistor and an information storage capacitor connected in series with each other: wherein the device comprises a semiconductor substrate (21) having a main surface in which a plurality of trenches (28) are formed, each of said trenches having an inner wall; wherein the cell selection transistor in one cell includes first and second doped regions (SR) formed in said main surface of said semiconductor substrate, said first doped region being connected with one data line (51), a first insulating film (35) formed on said main surface of said semiconductor substrate between said first and second doped regions, and a control electrode layer (36G) formed on said first insulating film between said first and second doped regions and connected with said one word line (36); wherein the information storage capacitor connected in series with the transistor to constitute said one cell includes a second insulating film (29) formed on the inner wall of one of said trenches, said second doped region of said transistor terminating at said inner wall of said one trench, an electrode layer (30) formed on said second insulating film and serving as a first electrode of said capacitor, a dielectric film (32) formed on said electrode layer, and a conducting material (33) provided to fill a space defined by said dielectric film in said one trench and serving as a second electrode of said capacitor; and wherein the device further comprises a conducting layer (42) extending both on said second doped region and said conducting material in said one cell to electrically interconnect them for the series connection.
Claim 2
Dependent Claim
55 words
A semiconductor integrated circuit device according to Claim 1, further comprising a third insulating film (43) formed on said conducting layer (42) and a first inter-layer film (48, 49) formed on said third insulating film to provide a substantially flat surface, said date line (55) extending on said flat surface of said first inter-layer film.
Claim 3
Dependent Claim
133 words
A semiconductor integrated circuit device according to Claim 1, wherein said word lines are formed with word line conductors (36) extending in a first direction, said data lines are formed with data line conductors (55) extending in a second direction substantially perpendicular to said first direction, and wherein the device further comprises a pattern of common potential conductors (330); shunt conductors (TL, SL) connected in parallel with said pattern of common potential conductors for enhancing electric conduction of the latter; and a plurality of transverse conducting layers (30') extending in a third direction not parallel with said first and second directions to traverse word line conductors and data line conductors, each of said transverse conducting layers interconnecting electrode layers for different plural ones of said capacitors and connected with said common potential conductors.
Claim 4
Dependent Claim
57 words
A semiconductor integrated circuit device according to Claim 1, wherein said second doped region of the cell selection transistor in said one memory cell terminating at said wall of said one trench has its terminating end in an electrical contact with said conducting material (33) on said wall of said one trench in said one memory cell.
Claim 5
Dependent Claim
53 words
A semiconductor integrated circuit device according to Claim 1, further comprising a doped layer (25) formed at a level deeper in said substrate than said first and second doped regions as seen from said main surface of said substrate and being in contact with said first insulating films (29) in said trenches (28).
Claim 6
Dependent Claim
169 words
A semiconductor integrated circuit device including a plurality of memory cells each having an information storage capacitor and a memory cell selecting MISFET connected in series, comprising: (a) a semiconductor substrate (21) of a first conductivity type having a plurality of trenches (28) in its principal surface; (b) a first insulating film (29) formed on a bottom and a side wall of each of said trenches; (c) a first electrode (30) formed on said first insulating film and adapted to have a predetermined fixed potential applied thereto; (d) a second insulating film (32) formed on said first electrode; (e) a second electrode (33) formed over said second insulating film; (f) a third electrode (36) formed over the principal surface of said semiconductor substrate through a third insulating film (35); and (g) first and second semiconductor regions (SR) of a second conductivity type formed in the principal surface of said semiconductor substrate at apposite ends of said third electrode, said second semiconductor region being electrically connected with said second electrode.
Claim 7
Dependent Claim
41 words
A semiconductor integrated circuit device according to Claim 6, wherein said first insulating film has such a thickness that an inversion layer is not formed on a surface of said semiconductor substrate by a fixed potential applied to said first electrode.
Claim 8
Dependent Claim
52 words
A semiconductor integrated circuit device according to Claim 7, wherein said third electrode (36) extends in a first direction to constitute a word line, and wherein said first semiconductor region is connected with a first wiring constituting a data line (51) and extending in a second direction perpendicular to said first direction.
Claim 9
Dependent Claim
26 words
A semiconductor integrated circuit device according to Claim 8, wherein said first wiring (51) is connected with said first semiconductor region through a fourth electrode (47).
Claim 10
Dependent Claim
28 words
A semiconductor integrated circuit device according to Claim 9, wherein said first wiring (51) is made of tungsten, and wherein said fourth electrode (47) is made of poly-silicon.
Claim 11
Dependent Claim
33 words
A semiconductor integrated circuit device according to Claim 8, wherein said first electrode (30) is connected with a second wiring (55) extending in said first direction and positioned over said first wiring (51).
Claim 12
Dependent Claim
19 words
A semiconductor integrated circuit device according to Claim 11, wherein said second wiring (55) is made mainly of aluminum.
Claim 13
Dependent Claim
33 words
A semiconductor integrated circuit device according to Claim 8, wherein said first insulating film (29) has a thickness about three times or more as large as that of said third insulating film (35).
Claim 14
Dependent Claim
76 words
A semiconductor integrated circuit device according to Claim 8, wherein said semiconductor substrate (21) is formed therein with a third semiconductor region (25) positioned below said first and second semiconductor regions (SR), and wherein said third semiconductor region has a conductivity type identical with that of said semiconductor substrate and a higher impurity concentration than that of said semiconductor substrate and contacts with said first insulating film (29) at the side walls of said trenches (28).
Claim 15
Dependent Claim
32 words
A semiconductor integrated circuit device according to Claim 8, wherein said first insulating film (29) extends from the side walls of said trenches (28) to the principal surface of said semiconductor substrate.
Claim 16
Dependent Claim
31 words
A semiconductor integrated circuit device according to Claim 15, wherein said second semiconductor region (SR) contacts with said first insulating film (29) at the principal surface of said semiconductor substrate (21).
Claim 17
Dependent Claim
39 words
A semiconductor integrated circuit device as set forth in Claim 6, further comprising a fifth electrode (42) for connecting said second electrode (33) and said second semiconductor region (SR) electrically at the principal surface of said semiconductor substrate (21).
Claim 18
Dependent Claim
20 words
A semiconductor integrated circuit device as set forth in Claim 17, wherein said fifth electrode (42) is made of poly-silicon.
Claim 19
Dependent Claim
46 words
A semiconductor integrated circuit device according to Claim 8, further comprising a band-shaped sixth electrodes (30') extending in a third direction transverse to said first and second directions for electrically connecting the first electrodes (30) of the information storage capacitors adjacent thereto in said second direction.
Claim 20
Dependent Claim
53 words
A semiconductor integrated circuit device according to Claim 19, wherein said plurality of memory cells constitute memory blocks, and wherein each of said sixth electrodes (30') is electrically connected with another sixth electrode in a common layer at a level of said sixth electrodes at an end portion of its associated memory block.
Claim 21
Dependent Claim
39 words
A semiconductor integrated circuit device according to Claim 20, wherein said sixth electrodes (30') are connected at the end portions of their associated memory blocks with layers (SL, TL) having a lower resistance than that of said sixth electrodes.
Claim 22
Dependent Claim
22 words
A semiconductor integrated circuit device according to Claim 6, wherein said trenches (28) have side faces substantially normal to said principal surface.
Claim 23
Dependent Claim
248 words
A process for manufacturing a semiconductor integrated circuit device including a plurality of memory cells each having a memory cell selection MISFET and an information storage capacitor connected in series, comprising the following steps of: (a) forming a plurality of trenches (28) in a surface of a semiconductor substrate (21); (b) forming a first insulating film (29) on a bottom and a side wall of each of said trenches; (c) forming a first electrode (30) on said first insulating film; (d) a second insulating film (32) for a dielectric film of said capacitors on the surface of said first electrode; (e) forming a second electrode (33) over said second insulating film in a manner to fill said trenches; (f) forming a third insulating film (34) over said second electrode in a manner to expose a portion of said second electrode; (g) forming a fourth insulating film (35) for a gate insulating film of said memory cell selection MISFETs on the surface of said semiconductor substrate and a third electrode (36, 36G) over said fourth and third insulating films; (h) forming first and second semiconductor regions (SR) in the surface of said semiconductor substrate in self-alignment with said third electrode; (i) forming a fifth insulating film (43) over and on the side wall of said third electrode; and (j) forming a fourth electrode (42) on the surface of said semiconductor substrate for connecting said second semiconductor region (SR) and said second electrode (33) in self-alignment with said third electrode.
References Cited (Backward Citations)
No citation records indexed.
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