Patent EP0514092A2 successfully refreshed from Google Patents.
EP0514092A2
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Information processing system
Assignee: Fujitsu Ltd
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Filing: 1992-05-08
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Granted: —
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Expires: 2012-05-08
Abstract
Abstract A processor including an instruction register which holds a plurality of user instruction codes one by one, a state counter which outputs a number indicating the internal state of a system which changes along with the execution of instructions, and a decoder which receives as input the contents of the instruction register and the state counter and produces various types of control signals for the system. The processor has two further units added. One is a detection/storage unit which detects the occurrence of predetermined specific processing and when detecting the same stores the specific instruction code preselected from among the abovementioned user instruction codes in the instruction register. The other is a state changing unit which, when there is a detection, presets the internal state number shown by the state counter to a certain value by force and which converts the instruction corresponding to the specific instruction code to an instruction compatible with the above-mentioned specific processing.
Inventors
- 👤 Takeshi c/o Fujitsu Limited Fuse
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 04:32
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/30; G06F9/38; G06F9/3861; G06F9/3017; G06F9/30181; G06F9/30189; G06F9/30196; G06F9/32; G06F9/322; G06F9/327
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
238 words
An information processing system comprising an instruction register (2) which sequentially receives a plurality of user instruction codes and stores and holds the user instruction codes while processing of the instructions corresponding to the user instruction codes received is being executed, a state counter (3) which outputs a number showing the internal state of the system, which changes in accordance with the incrementing of the steps of the processing due execution of processing of instructions corresponding to the user instruction codes stored and held in the above-mentioned instruction register, and a decoder (4) which receives as input the user instruction codes stored and held in the above-mentioned instruction register and the above-mentioned internal state number indicated by the above-mentioned state counter and generates various types of control signals for different portions in the system based on these value, wherein the said system further includes the following constituent elements: a detection/storage means (10) which detects when a predetermined specific processing operation must be executed in the system and stores a specific instruction code preselected from the plurality of user instruction codes in the above-mentioned instruction register and a state changing means (20) which cooperates with the above-mentioned state counter and changes the above-mentioned internal state number of the state counter when the above-mentioned detection and storage are performed so as to convert the specific instruction code to another instruction code which cannot be defined by the user instruction codes.
Claim 2
Dependent Claim
49 words
A system as set forth in claim 1, wherein said state counter (3) increments the said internal state number from 0 for the user instruction codes, while the state changing means (20) controls the state counter so as to increment from a predetermined internal state number of 0 on.
Claim 3
Dependent Claim
40 words
A system as set forth in claim 2, wherein said state changing means (20) operates so as to increment from an internal state number which does not overlap with the internal state number which the above-mentioned specific instruction code uses.
Claim 4
Dependent Claim
49 words
A system as set forth in claim 3, wherein said state changing means (20) operates so that the final internal state number which said specific instruction code uses and the final internal state number which the other instruction code converted from said specific code uses are made to match.
Claim 5
Dependent Claim
34 words
A system as set forth in claim 1, wherein said specific instruction code is selected from among user instruction codes with small numbers of internal states among the said plurality of user instruction codes.
Claim 6
Dependent Claim
27 words
A system as set forth in claim 1, wherein said state changing means (20) is activated when there is a detection by the said detection/storage means (10).
Claim 7
Dependent Claim
36 words
A system as set forth in claim 1, wherein the occurrence of said predetermined specific processing is detected outside of the system and the detection signal is used to activate the said state changing means (20).
Claim 8
Dependent Claim
83 words
A system as set forth in claim 1, wherein: said detection/storage means (10) detects an interrupt request as said specific processing, by that detection, stops once the transfer of the next user instruction code to the said instruction register (2), and stores the specific instruction code preallocated to the interrupt processing in the said instruction register and said state changing means (20) is set so that the internal state shown by the said state counter (3) complies with the said interrupt processing state.
Claim 9
Dependent Claim
17 words
A system as set forth in claim 8, wherein said specific instruction code is a "jump" instruction.
Claim 10
Dependent Claim
83 words
A system as set forth in claim 1, wherein said detection/storage means (10) detects a reset input as said specific processing, by that detection, stops once the transfer of the next user instruction code to the said instruction register (2), and stores the specific instruction code preallocated to the reset processing in the said instruction register and said state changing means (20) is set so that the internal state shown by the said state counter (3) complies with the said reset processing state.
Claim 11
Dependent Claim
19 words
A system as set forth in claim 10, wherein said specific instruction code is a "no operation" (NOP) instruction.
Claim 12
Dependent Claim
151 words
A system as set forth in claim 2, wherein said state counter (3) and said state changing means (20) are basically comprised of a plurality of counter cells (31), OR gates (23), and multiplexers (24) connected in cascade by carry-in (Cin) terminals and carry-out (Cout) terminals, output (Q) terminals of the said counter cells are connected to the input of the said decoder (4), write terminals of said counter cells are connected to the outputs of the said OR gates receiving as two inputs the load signal from said decoder and the detection signal from said detection/storage means (10), and data terminals of said counter cells are connected in BIT correspondence with the output of the said multiplexers which selectively output the load data BITS output together with the load signal from the said decoder and BITS showing the predetermined internal state number after 0 output together with said detection signal.
Claim 13
Dependent Claim
47 words
A system as set forth in claim 12, wherein said counter cells (31) incorporate D-flip-flops (32) and other multiplexers (33) are incorporated which selectively apply the signal from the said carry-in terminal or the signal from said carry-out signal to the data input terminals of the D-flip-flops.
Claim 14
Dependent Claim
56 words
A system as set forth in claim 13, wherein functions corresponding to pairs of a counter cell (31) and a multiplexer (24) are realized by the counter cells (35) for the asynchronous forced reset input terminals and wherein BITs showing the predetermined internal state number after 0 are preset in BIT correspondence in the counter cells.
References Cited (Backward Citations)
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