Patent EP0511628A2 successfully refreshed from Google Patents.
EP0511628A2
Expired / Lapsed
EP
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Insulator for integrated circuits formed by high-pressure oxidation
Assignee: Texas Instruments Inc
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Filing: 1992-04-28
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Granted: —
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Expires: 2012-04-28
Abstract
Abstract A non-volatile memory array is formed on a semiconductor layer of a first conductivity-type. Polysilicon insulated floating gates are formed over and insulated from channel regions in the surface of the semiconductor layer. Control gates are formed over and insulated from the floating gates. An inter-level insulator between each floating gate and control gate has first oxide layer over the floating gate and a silicon nitride layer over the first oxide layer. High-pressure-oxidation converts the upper portion of the silicon nitride to silicon-oxide-nitride.
Inventors
- 👤 Manzur Gill
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 11:54
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/65; H10P14/6516; H10P14/6518; H10P14/6519; H10P14/6522; H10B; H10B41/00; H10B41/30; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10P14/66; H10P14/662; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/694; H10P14/6943; H10P14/69433
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
63 words
A method for fabricating an insulator on a doped polysilicon layer at a face of a semiconductor layer of a first conductivity-type, comprising: forming an oxide insulator layer on said doped polysilicon layer; depositing a layer of silicon nitride over said first oxide insulator layer; and using a high-pressure-oxidation Process to grow a graded silicon dioxide/silicon nitride layer over said silicon nitride layer.
Claim 2
Dependent Claim
28 words
The method of Claim 1, including depositing a silicon dioxide layer over said deposited silicon nitride layer, wherein said high-pressure-oxidation process grows a silicon dioxide/graded silicon dioxide/nitride layer.
Claim 3
Dependent Claim
22 words
The method of Claim 1, including forming a gate insulator layer over said semiconductor layer prior to forming said doped polysilicon layer.
Claim 4
Dependent Claim
45 words
The method of Claim 1, including selectively doping said semiconductor layer with at least one dopant of a second conductivity-type opposite said first conductivity-type to create drain-column lines including drains and to create source-column lines including sources, said sources spaced from said drains by channels.
Claim 5
Dependent Claim
76 words
The method of Claim 1, including selectively doping said semiconductor layer with at least one dopant of a second conductivity-type opposite said first conductivity-type to create drain-column lines including drains and to create source-column lines including sources, said sources spaced from said drains by channels; and differentially growing first thermal insulator regions over said drain-column lines and second thermal insulator regions over said source-column lines such that said sources diffuse beyond said second thermal insulator regions.
Claim 6
Dependent Claim
105 words
The method of Claim 1, including selectively doping said semiconductor layer with at least one dopant of a second conductivity-type opposite said first conductivity-type to create drain-column lines including drains and to create source-column lines including sources, said sources spaced from said drains by channels; and differentially growing first thermal insulator regions over said drain-column lines and second thermal insulator regions over said source-column lines such that said sources diffuse beyond said second thermal insulator regions; forming thick field insulator regions prior to said selective doping step, said thick field oxide region positioned between said channel regions and between said source-column and said drain-column lines.
Claim 7
Dependent Claim
21 words
The method of Claim 1, including selectively etching said doped polysilicon layer and said insulator layer to define floating gate strips.
Claim 8
Dependent Claim
31 words
The method of Claim 1, including selectively etching said doped polysilicon layer and said insulator layer to define floating gate strips; and forming a second doped polysilicon layer over said face.
Claim 9
Dependent Claim
53 words
The method of Claim 1, including selectively etching said doped polysilicon layer and said insulator layer to define floating gate strips; forming a second doped polysilicon layer over said face; and selectively etching said second doped polysilicon layer, said insulator layer and said floating gate strips to define row lines and floating gates.
Claim 10
Dependent Claim
88 words
A nonvolatile memory cell, comprising: a semiconductor layer of a first conductivity-type; a polysilicon insulated floating gate over and insulated from a channel region in the surface of said semiconductor layer; a control gate over and insulated from said floating gate; and an inter-level insulator between said floating gate and said control gate, said inter-level insulator comprising a first oxide layer over said floating gate, a deposited silicon nitride layer over said first oxide layer and a high-pressure-oxidation-grown graded silicon dioxide/silicon nitride layer over said silicon nitride layer.
Claim 11
Dependent Claim
98 words
A nonvolatile memory array, comprising: a semiconductor layer of a first conductivity-type; polysilicon insulated floating gates, each floating gate over and insulated from a channel region in the surface of said semiconductor layer; control gates, each control gate over and insulated from a said floating gate; and inter-level insulators, each inter-level insulator between a said floating gate and a said control gate, each said inter-level insulator comprising a first oxide layer over said floating gate, a deposited silicon nitride layer over said first oxide layer, and a high-pressure-oxidation-grown graded silicon oxide/nitride layer over said deposited silicon nitride layer.
Claim 12
Dependent Claim
33 words
The structure of either of Claims 10 or 11, including source and drain regions at each end of said channel region, wherein said source and drain regions are buried under thermal insulator regions.
Claim 13
Dependent Claim
47 words
The structure cell of either Claims 10 or 11, including source and drain regions at each end of said channel region, wherein said source and drain regions are buried under thermal insulator regions and wherein said floating gate extends at least partially over said thermal insulator regions.
Claim 14
Dependent Claim
21 words
The structure cell of either of Claims 10 or 11, including at least one thick field insulator region adjacent said channel.
References Cited (Backward Citations)
No citation records indexed.
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