Patent EP0510705A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0510705A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Field effect transistor

Assignee: Sumitomo Electric Industries Ltd
•
Filing: 1992-04-26
•
Granted: —
•
Expires: 2012-04-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract According to the invention, a FET includes an epitaxially grown n-type GaInAs channel layer (4), first and second undoped GaInAs layers (3, 5) formed to sandwich the channel layer (4), a buffer layer (2) formed on a GaAs substrate (1) to be in contact with one side of the first layer (3), and a cap layer (6) formed to be in contact with one side of the second layer (5). At this time, each of the first and second undoped GaInAs layers (3, 5) must be formed as a graded layer in which the In composition ratio is gradually varied such that the In composition ratio is high on the channel layer side and is low on the buffer layer side and the cap layer side. If the first and second layers (3, 5) and the channel layer (4) are uniform layers each having a constant In composition ratio, a total film thickness of the three layers constituted by the first layer (3), the channel layer (4) and the second layer (5) must be smaller than a critical film thickness at which dislocation is caused by lattice distortion. In either case, a region in which carrier electrons are present is not entirely located on the channel layer (4), but a part of the region extends to the undoped GaInAs layers. For this reason, carrier electrons present in the undoped GaInAs layers are not scattered by dopant atoms, and the carrier electrons are permitted to move at high speed, thereby decreasing the source resistance and increasing the transconductance (g m ). In addition, a high-speed operation with low noise can be achieved.

Inventors

  • 👤 Nobuhiro C/O Yokohama Works Of Kuwata

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-06 19:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/801; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 126 words
A field effect transistor comprising: an epitaxially grown n-type GaInAs channel layer (4); first and second undoped GaInAs layers (3, 5) formed to sandwich said channel layer (4); a buffer layer (2) formed by a semiconductor having a band gap higher than that of said first layer (3) to be lattice-matched with said first layer (3) and to be in contact with one side of said first layer (3); a cap layer (6) formed by a semiconductor having a band gap higher than that of said second layer (5) to be lattice-matched with said second layer (5) and to be in contact with one side of said second layer (5); and a gate electrode (7) formed to be in Schottky contact with said cap layer (6).
Claim 2
Dependent Claim 55 words
A transistor according to claim 1, wherein each of said first and second layers (3, 5) is a graded layer in which an In composition ratio is gradually varied such that an In composition ratio is high on said channel layer side and is low on said buffer layer side and said cap layer side.
Claim 3
Dependent Claim 48 words
A transistor according to claim 1 or 2, wherein In composition ratios of said first and second layers (3, 5) are equal to an In composition ratio of said channel layer (4) on junction surfaces between said channel layer (4) and said first and second layers (3, 5).
Claim 4
Dependent Claim 35 words
A transistor according to claim 1, wherein said buffer layer (2) is formed on a semi-insulating substrate (1), said semi-insulating substrate being preferably made of GaAs and said buffer layer being preferably made of GaAs.
Claim 5
Dependent Claim 28 words
A transistor according to any of the proceding claims, wherein said cap layer (6) is made of one member selected from the group consisting of GaAs and AlGaAs.
Claim 6
Dependent Claim 90 words
A transistor according to claim 1, wherein said buffer layer (2) is made of GaAs, said first layer (3) is a graded layer in which an In composition ratio is gradually varied such that an In composition ratio is high on said channel layer side and is low on said buffer layer side, and an In composition ratio of said first layer (3) is substantially equal to an In composition ratio of said buffer layer (2) on a junction surface between said buffer layer (2) and said first layer (3).
Claim 7
Dependent Claim 100 words
A transistor according to claim 1, wherein said cap layer (6) is made of one member selected from the group consisting of GaAs and AlGaAs, said second layer (5) is a graded layer in which an In composition ratio is gradually varied such that an In composition ratio is high on said channel layer side and is low on said cap layer side, and an In composition ratio of said second layer (5) is substantially equal to an In composition ratio of said cap layer (6) on a junction surface between said cap layer (6) and said second layer (5).
Claim 8
Dependent Claim 27 words
A transistor according to claim 1, wherein each of said first and second layers (3, 5) is a uniform layer having a substantially constant In composition ratio.
Claim 9
Dependent Claim 32 words
A transistor according to claim 8, wherein the In composition ratios of said first and second layers (3, 5) are substantially equal to an In composition ratio of said channel layer (4).
Claim 10
Dependent Claim 44 words
A transistor according to claim 9, wherein a total film thickness of three layers constituted by said first layer (3), said channel layer (4) and said second layer (5) is smaller than a critical film thickness at which dislocation is caused by lattice distortion.
Claim 11
Dependent Claim 90 words
A transistor according to claim 1, wherein said buffer layer (2) is made of GaAs, said cap layer (6) is made of one member selected from the group consisting of GaAs and AlGaAs, said first and second layers (3, 5) are made of undoped Ga 0.85 In 0.15 As, said channel layer (4) is made of Ga 0.85 In 0.15 As doped with an n-type impurity, and a total film thickness of three layers constituted by said first layer, said channel layer and said second layer is about 150 Å.
Claim 12
Dependent Claim 60 words
A transistor according to claim 1, wherein, when the sum of a Ga composition ratio and an In composition ratio is set to be 1, an In composition ratio of GaInAs for forming said channel layer (4) is not less than 0.1 and not more than 0.3, said channel layer (4) being preferably made of Ga 0.85 In 0.15 As.
Claim 13
Dependent Claim 31 words
A transistor according to any of the proceding claims, further comprising a source electrode (8) and a drain electrode (9) formed to be in ohmic contact with said cap layer (6).
Claim 14
Dependent Claim 62 words
A transistor according to any of claims 1 to 12, wherein contact layers (11) are formed on said cap layer (6), and a source electrode (8) and a drain electrode (9) are formed on said contact layers (11), said contact layers being preferably made of one member selected from the group consisting of GaAs doped with Si and GaInAs doped with Si.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag