Patent EP0073568A1 successfully refreshed from Google Patents.
Patent EP0510607B1 successfully refreshed from Google Patents.
EP0510607B1
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Canon Inc
•
Filing: 1992-04-22
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Granted: 1998-02-04
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Expires: 2012-04-22
Abstract
No abstract record available.
Inventors
- 👤 Mamoru C/O Canon Kabushiki Kaisha Miyawaki
- 👤 Akira C/O Canon Kabushiki Kaisha Ishizaki
- 👤 Genzo c/o Canon Kabushiki Kaisha Monma
- 👤 Hiroshi C/O Canon Kabushiki Kaisha Yuzurihara
- 👤 Tetsunobu C/O Canon Kabushiki Kaisha Kohchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:15
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/62; H10D30/6211; H10B; H10B12/00; H10B12/30; H10B69/00; H10D30/01; H10D30/021; H10D30/024; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0149; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
171 words
A semiconductor memory device comprising: an insulated gate type transistor including a source electrode
region (1008; 1030) and a drain electrode region (1006; 1017)
and a channel region (1021) provided between said source and
drain electrode regions (1008, 1006; 1030, 1017), and a gate
electrode (1007; 1023; 1068, 1069) provided on said channel
region (1021) with a gate insulator (1022) provided therebetween;
and an electrically breakable memory element (1009'; 1031'; 1041')
provided on one of said source and drain electrode regions
(1008, 1006; 1030, 1017); characterized in that a semiconductor region (1016) is provided below and in contact
with said channel region (1022), said semiconductor region
(1016) having the same conductivity type as that of said channel
region (1021) and a higher impurity concentration than said
channel region (1021); and said gate electrode (1007; 1023; 1068, 1069) and said semiconductor
region (1016) provided adjacent to said channel region
(1021) in combination enclose at least four surfaces of said
channel region (1021) which run in a direction in which carriers
are mobilized.
Claim 2
Dependent Claim
55 words
A semiconductor memory device according to claim 1, characterized
by further comprising a second semiconductor region (1080) provided on the surface of
said channel region (1021) which is remote from said semiconductor
region (1016) and has the same conductivity type as said
channel region (1021) and a higher impurity concentration than
said channel region (1021).
Claim 3
Dependent Claim
70 words
A semiconductor memory according to claim 1, characterized
by further comprising a third semiconductor region (1085) provided between said
source and drain electrode regions (1008, 1006; 1030, 1017) and
said channel region (1021), said third semiconductor region
(1085) having the same conductivity type as said source and
drain electrode regions (1008, 1006; 1030, 1017) and a lower
impurity concentration than said source and drain electrode
regions (1008, 1006; 1030, 1017).
Claim 4
Dependent Claim
44 words
A semiconductor memory device according to any of the preceding
claims 1 to 3, characterized in that said memory element (1009'; 1031'; 1041') has a semiconductor
layer; and writing is performed by breaking a junction between said semiconductor
layer and another layer adjoining thereto.
Claim 5
Dependent Claim
37 words
A semiconductor memory device according to any of the preceding
claims 1 to 4, characterized by further comprising an interconnection for a power source which runs in a direction
of the source and drain of said transistor.
Claim 6
Dependent Claim
40 words
A semiconductor memory device according to any of the preceding
claims 1 to 4, characterized in that an interconnection for a power source is disposed in a direction
which crosses a direction of the source and drain of said
transistor.
Claim 7
Dependent Claim
98 words
A semiconductor memory device, characterized in that a plurality of memory devices according to any of the preceding
claims 1 to 4 is provided, said plurality of memory devices
being matrix connected to each other by a plurality of first
interconnections (1001, 1001' 1001'') which are common to the
gate electrodes of said plurality of memory devices, and a
plurality of second interconnections (1002, 1002', 1002'';
1025; 1032; 1082) which are common to the memory elements of
said plurality of memory devices, a power source line being
disposed between adjacent second interconnections (1002, 1002',
1002''; 1025; 1032; 1082).
Claim 8
Dependent Claim
27 words
A semiconductor memory device according to claim 1, characterized
in that said semiconductor region (1016) has a portion sandwiched between
a part of said gate electrode (1023).
References Cited (Backward Citations)
No citation records indexed.
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