Stacked etch fabrication of cross-point EPROM arrays

Claim 1

A method of stacked etch fabrication of an EPROM array including cross-point cells with internal access transistors and polysilicon floating gates overlying channel regions between source and drain regions and a polysilicon word line, characterised in that the edges of the floating gates parallel to the word line are self-aligned to the word line such as to eliminate parasitic polysilicon transistors.

Claim 2

A method of fabricating a cross-point EPROM array in a P-type silicon substrate, the array including a cell array area and a peripheral area, the method comprising: (a) forming a first layer of insulating material on the silicon substrate; (b) forming a first layer of polysilicon on the layer of insulating material; (c) forming a second layer of insulating material on the first layer of polysilicon; (d) forming a mask to define parallel lines of the second insulating material and underlying first layer of polysilicon; (e) etching exposed portions of the second insulating layer and underlying first layer of polysilicon to define parallel vertical strips of the second layer and the polysilicon; (f) after removing the mask, forming N+ regions in the silicon substrate between the parallel vertical strips; (g) performing a differential oxidation step to form additional oxide on the second insulating material of the vertical strips while simultaneously forming oxide over the N+ regions; (h) forming a protect array mask for protecting the cell array area; (i) removing the second layer of insulating material and underlying polysilicon and first layer of insulating material from the peripheral area; (j) after removing the protect array mask, forming gate oxide regions in the peripheral area; (k) forming a second layer of polysilicon over the structure formed in steps (a)-(j) above; (l) forming a layer of conductive material over the second layer of polysilicon; (m) forming a polysilicon mask on the layer of conductive material to define parallel lines of polysilicon 2 that run perpendicular to the polysilicon vertical strips; (n) etching the conductive material and the underlying polysilicon to define polysilicon word lines running perpendicular to the polysilicon strips but separated therefrom by the insulating material of the said second layer; (o) forming a self aligned etch mask over the polysilicon mask in the peripheral area; and (p) utilizing the polysilicon word lines in a stacked etch step to define polysilicon floating gates at the cross-point EPROM cells of the array.

Claim 3

A method of fabricating a cross-point EPROM array in a silicon substrate of P-type conductivity, the array including a cell array area and a peripheral area, the method comprising: (a) forming a layer of first insulating material on the silicon substrate; (b) forming a first layer of polysilicon (polysilicon 1) on the layer of insulating material; (c) forming a layer of second insulating material on the first layer of polysilicon; (d) forming a polysilicon 1 mask to define parallel lines of the second insulating material and underlying first layer of polysilicon; (e) etching exposed portions of the second insulating material and underlying first layer of polysilicon to define parallel vertical strips of second insulating material and polysilicon 1; (f) after removing the polysilicon 1 mask, forming N+ regions in the silicon substrate between the parallel vertical strips of second insulating material and polysilicon 1; (g) performing a differential oxidation step to form additional oxide on the second insulating material of the vertical strips while simultaneously forming oxide over the N+ regions; (h) forming a protect array mask for protecting the cell array area; (i) removing the second insulating material, and underlying polysilicon 1 and first insulating material from the peripheral area; (j) after removing the protect array mask, forming gate oxide regions in the peripheral area; (k) forming a second layer of polysilicon (polysilicon 2) over the structure formed in steps (a)-(j) above; (l) forming a layer of conductive material over the second layer of polysilicon; (m) forming a polysilicon 2 mask on the layer of conductive material to define parallel lines of polysilicon 2 that run perpendicular to the polysilicon 1 vertical strips; (n) etching the conductive material and the underlying polysilicon 2 to define polysilicon 2 word lines running perpendicular to the polysilicon 1 strips but separated therefrom by the second insulating material. (o) forming a self aligned etch mask over the polysilicon 2 mask in the peripheral area; (p) utilizing the polysilicon 2 word lines in a stacked etch step to define the polysilicon 1 floating gates at the cross-point EPROM cells of the array.