Patent EP0509135A1 successfully refreshed from Google Patents.
EP0509135A1
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Propulsion control system central processing unit board
Assignee: Bombardier Transportation Holdings USA Inc
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Filing: 1991-09-23
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Granted: —
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Expires: 2011-09-23
Abstract
Abstract For use in a propulsion control system, a microprocessor based central processing unit board includes both Multibus I and Multibus II interfaces. Multibus I master interface and Multibus slave interface controllers are designed for high data throughput by using programmed logic design (PLD) technology. In addition, the need for latching of data transceivers used in conventional Multibus I designs is eliminated. The Multibus II interface is removable.
Inventors
- 👤 William F. Molyneaux
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:48
CPC Classifications
B; B60; B60L; B60L9/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
322 words
A propulsion control system for controlling a vehicle comprising: a field connector interface board connected to vehicle wiring; a plurality of master and slave interface and control boards connected to the field connector interface board, including a digital input-output board, an analog input-output board, a bitbus board, a tach reader board, a memory board, and a master CPU board; a first bus connected to the plurality of master and slave interface and control boards and a second bus connected to the master CPU board; wherein, the master CPU board comprises: a local bus; memory; special purpose devices; a central processing unit operatively connected to said memory and special purpose devices by said local bus, said special purpose devices including a multifunction peripheral device, having: wait state generator means for generating timing signals, direct memory access control means for controlling data transfer in said system, and interrupt handling means for generating interrupt requests and handling direct memory access interrupts; a first bus interface, operatively connected to said multifunction peripheral device and said local bus, including: first bus master control logic means for controlling the first bus responsive to said interrupt requests from said interrupt handling means; and buffering means for buffering data between said local bus and the first bus responsive to said first bus control logic means; and a second bus interface, operatively connected to said multifunction peripheral device, including: second bus master control logic means for controlling the second bus and producing said direct memory access interrupts; interconnect means for interfacing control signals from said second bus control logic means; reset control having an output connected to said interconnect means; and buffering means for buffering data between the second bus and said second bus control logic means responsive to control signals from said interconnect means; whereby said central processing unit circuit board is able to communicate with other components of said propulsion control system via said first and said second buses.
Claim 2
Dependent Claim
244 words
A central processing unit circuit board comprising: a local bus; memory; special purpose devices; a central processing unit operatively connected to said memory and special purpose devices by said local bus, said special purpose devices including a multifunction peripheral device, having: wait state generator means for generating timing signals, direct memory access control means for controlling data transfer in said system, and interrupt handling means for generating interrupt requests and handling direct memory access interrupts; a first bus interface, operatively connected to said multifunction peripheral device and said local bus, including: first bus master control logic means for controlling a first external bus responsive to said interrupt requests from said interrupt handling means; and buffering means for buffering data between said local bus and the first external bus responsive to said first bus control logic means; and a second bus interface, operatively connected to said multifunction peripheral device, including: second bus master control logic means for controlling a second external bus and producing said direct memory access interrupts; interconnect means for interfacing control signals from said second bus control logic means; reset control having an output connected to said interconnect means; and buffering means for buffering data between the second external bus and said second bus control logic means responsive to control signals from said interconnect means; whereby said central processing unit circuit board is able to communicate with other components of said propulsion control system via said first and said second external buses.
Claim 3
Dependent Claim
110 words
The central processing unit circuit board of claim 2, wherein said first bus master control logic means for controlling the first external bus comprises: bus control logic means for producing timing and control signals; arbiter means, responsive to said timing and control signals, for providing multi-master bus protocol control and synchronization of the central processor with the first external bus; decoder means, responsive to said timing and control signals, for enabling said master bus logic device responsive to address signals from the central processor; and latch control means, responsive to said timing and control signals, for generating command and control timing for the first external bus to optimize its performance.
Claim 4
Dependent Claim
293 words
For use with the master CPU board of claim 2, a slave controller for connection to the first bus master control logic means by an external bus via address, data and control lines, said slave controller comprising: address buffering means for buffering, inverting and latching a plurality of address lines; board address decoder comprised of a programmed logic device; buffering means for buffering control bus signals from the bus master control logic means; board enable signal generating means for generating a board enable signal indicating slave board access during a present bus cycle; data buffering means for buffering data, enabled and disabled by the board enable signal D-type flip-flop means for synchronizing the board enable signal generating means with a timing clock, and for keeping the board enable signal high by feeding an inverted output of said board enable signal generating means back to a reset input thereof; slave control logic means having a plurality of registered outputs, a first plurality forming a mode state machine which is clocked by the rising edges of a timing reference, a second plurality producing on-board control signals, and having a plurality of inputs used to input control signals, said slave control logic means generating read and write strobes for the slave board only, and when a read or write operation is completed, signaling completion to the bus master control logic means; and NAND means for combining read and write strobes to produce an output to a clear line of said board enable signal generating means to remove the board enable signal once said read or said write strobe is no longer asserted, whereby, by using the read or write strobe to clear the board enable signal, it is ensured that all the bus cycles are received.
Claim 5
Dependent Claim
19 words
The central processing unit circuit board of claim 2, wherein: said second bus interface is removable from said board.
Claim 6
Dependent Claim
116 words
A bus master logic device for controlling a multi-master bus in a system which includes a central processor, comprising: bus control logic means for producing timing and control signals for the multi-master bus; arbiter means, responsive to said timing and control signals, for performing bus arbitration, including providing multi-master bus protocol control and synchronization of the central processor with the multi-master bus; decoder means, responsive to said timing and control signals and to address signals from the central processor for enabling said bus master logic device; and latch control means, responsive to said timing and control signals, for performing bus control functions, including command and control timing generation for the multi-master bus to optimize bus performance.
References Cited (Backward Citations)
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