An echo canceller

Claim 2

(2) An echo canceller according to claim 1, wherein said convergence control processor (24) chooses an operation mode from an ordinary mode, an accumulating mode, or a reset mode according to the situation of said sub echo estimator (22) determined by levels of at least said main and sub residual echoes, said accumulating mode is chosen under a convergent situation of said sub echo estimator (22), said reset mode is chosen under a divergent situation of said sub echo estimator (22), and said ordinary mode is chosen under the other situation in which said sub echo estimator (22) does not converge and diverge, in said ordinary mode, said filter coefficients in said main and sub echo estimators (21, 22) are updated according to said receive input signal and said main and sub residual echoes, respectively, and in said accumulating mode, said filter coefficients in said sub echo estimator (22) are accumulated on said related filter coefficients in said corresponding main echo estimator (21 ) through said register accumulator (23) and after reset of said filter coefficients in said convergent sub echo estimator (22), the mode is switched to said ordinary mode, and in said reset mode, said filter coefficients in said divergent sub echo estimator (22) are reset, and then the mode is switched to said ordinary mode.

Claim 3

(3) An echo canceller according to claim 1, wherein said subtracter (25, 431) coupled with said main echo estimator (21, 421) is followed by cascaded subtracters (26, 432, 433), each of which is coupled with a sub echo estimator (22, 422, 423), said subtracter (431) outputs said main residual echo to said cascaded subtracter (432) and to said transmit output port (8) by subtracting an estimate given by said main echo estimator (421) from said transmit input signal, and sub echo estimators (422, 423) provide respectively estimates to said related sub subtracters (432, 433) to obtain sub residual echoes, and a register control processor (41) comprising said convergence control processor (24) and said register accumulator (23) controls said main and sub echo estimators (421, 422, 423) and said register accumulator according to the situations of said sub echo estimators (422, 423) determined by levels of at least said main and sub residual echoes, said register control processor (41) determines the operation mode either to update said filter coefficients in each of echo estimators (421, 422, 423) in an ordinary mode, to accumulate said filter coefficients in convergent sub echo estimator (422, 423) on said related filter coefficients in said main echo estimator (421) and then reset filter coefficients in said convergent sub echo estimators in an accumulating mode, or to reset said filter coefficients in divergent sub echo estimators in a reset mode.

Claim 4

(4) An echo canceller according to claim 1, wherein said subtracter (25, 531) coupled with said main residual echo estimator (21, 521) is followed by a plurality of subtracters (532, 533) in parallel, each of which is coupled with a sub echo estimator and outputs a sub residual echo, at said subtracter (531) said main residual echo is obtained by subtracting an estimate given by said main echo estimator (521) from said transmit input signal, the sub residual echoes are obtained respectively by subtracting estimates given by said sub echo estimators (522, 523) from said main residual echo, and a register control processor (51) comprising said convergence control processor and said register accumulator controls these echo estimators (521, 522, 523) and said register accumulator according to the situations of said sub echo estimators (522, 523) determined by levels of at least said main and sub echo residual echoes, said register control processor (51) determines the operation mode either to update said filter coefficients in each of echo estimators (521, 522, 523) in an ordinary mode, to accumulate said filter coefficients in convergent sub echo estimator on said related filter coefficients in said main echo estimator (521) and then reset filter coefficients in said convergent sub echo estimators in an accumulating mode, or to reset said filter coefficients in divergent sub echo estimators in a reset mode.

Claim 5

(5) An echo canceller according to claim 1, wherein said subtracter (25, 631) coupled with said main echo estimator (21, 621) is followed by a plurality of subtracters in cascade or in parallel, each of which is coupled with a sub echo estimator and outputs a sub residual echo, said main residual echo at said subtracter (631) is obtained by subtracting an estimate given by said main echo estimator (621) from said transmit input signal, and a subtracter (632) in parallel with said subtracter (631) is coupled with a sub estimator (622) and is followed by a plurality of subtracters in cascade or in parallel, each of which is coupled with a sub echo estimator and outputs a sub residual echo, and a register control processor (61) comprising said convergence control processor and said register accumulator controls these echo estimators (621, 622, 623, 624) and said register accumulator according to the situations of said sub echo estimators (622, 623, 624) determined by levels of at least said main and sub residual echoes, said register control processor (61) determines the operation mode either to update said filter coefficients in each of echo estimators (621, 622, 623, 624) in an ordinary mode, to accumulate said filter coefficients in convergent sub echo estimator (623) on said related filter coefficients in said corresponding main echo estimator (621) and/or to accumulate said filter coefficients in convergent sub echo estimator (624) on said related filter coefficients in said corresponding sub echo estimator (622) and then reset said filter coefficients in said convergent sub echo estimators (623, 624) at said register accumulator in an accumulating mode, to transfer said filter coefficients in said sub echo estimator (622) to said related filter coefficients in said main echo estimator (621) and then reset said filter coefficients in said sub echo estimator (622) in a transfer mode, or to reset said filter coefficients in divergent sub echo estimators (623, 624) in a reset mode.

Claim 6

(6) An echo canceller according to claim 1, wherein a plurality of subtracters (731, 732, 733, 734) is coupled in cascade, and each of them is coupled with either a main echo estimator (721, 722) or a sub echo estimator (723, 724), a plurality of delay units is also provided for compensating the delay in an echo path, which exceeds the range of the delay covered by the echo estimator, said receive input signal is fed to a pair of said main echo estimator (721) at the first stage and the related sub echo estimator (723) which are coupled with the delay unit (741) having a fixed delay corresponding to the inherent delay of said echo path, and is also to a pair of said main echo estimator (21, 722) and the related sub echo estimators (724) coupled with the delay unit (742) having a delay corresponding to the total delay in said main echo estimator (721) at the front stage and the delay unit(741) coupled with it, an output of the first subtracter (731) obtained by subtracting an estimate given by said main echo estimator (721) at the first stage from said transmit input signal is fed to the following subtracter (25, 732), said subtracter (25, 732) coupled with said main echo estimator (722) at the last stage provides said main residual echo to said transmit output port (8), to said main echo estimators (721, 722) for updating filter coefficients and to said following subtracter (733) coupled with said sub echo estimator (723), said sub residual echo at the last subtracter (734) is fed to said sub estimators (723, 724) for updating filter coefficients, a register control processor (71) comprising said convergence control processor and said register accumulator controls these echo estimators (721, 722, 723, 724) and said register accumulator according to the situations of said sub echo estimators (723, 724) determined by levels of at least main and sub residual echoes, said register control processor (71) determines the operation mode either to update filter coefficients in each of echo estimators (721, 722, 723, 724) in an ordinary mode, to accumulate said filter coefficients in convergent sub echo estimator on related filter coefficients in said corresponding main echo estimator (721, 722) through said register accumulator and then reset said filter coefficients in said convergent sub echo estimator in an accumulating mode, or to reset said filter coefficients in divergent sub echo estimator in a reset mode.

Claim 7

(7) An echo canceller according to claim 1, wherein subband filters (841, 842) are provided for dividing bandwidths of the receive and transmit input signals to a plurality of subbands to obtain subband transmit and receive input signals, a combiner (85) is provided for synthesizing said transmit output signal having an original band with subband main residual echoes, a plurality of main echo estimators (821, 822) is provided for obtaining estimates of the subband transmit input signals, and each of them is coupled with a subtracter (831, 832) which outputs the subband main residual echo for the corresponding subband, a plurality of sub echo estimators (823, 824) is provided for obtaining estimates of the subband main residual echoes, respectively, and each of them is coupled with a subtracter (833, 834) which outputs a subband sub residual echo for the corresponding subband, a register control processor (81) comprising said convergence control processor and said register accumulator is provided for controlling main and sub echo estimators (821, 822, 823, 824) and said register accumulator according to the situations of said sub echo estimators (823, 824) determined by levels of at least said subband main and sub residual echoes for the subbands, said register control processor (81) chooses the operation modes for the subbands from an ordinary mode, an accumulating mode and a reset mode according to the respective situations of said sub echo estimators (823, 824), according to the control signals from said register control processor (81), filter coefficients in said main and sub echo estimators (821, 822, 823, 824) are updated in said ordinary mode, respectively, filter coefficients in convergent sub echo estimator are accumulated respectively on said related filter coefficients in said corresponding main echo estimator (821, 822) through said register accumulator and then are reset in said accumulating modes, and filter coefficients in divergent sub echo estimator (823, 824) are reset in said reset mode.

Claim 8

(8) An echo canceller according to claims 1 - 7, wherein a step gain for coefficient updating in said main echo estimator (21) is equal or smaller than a step gain in said corresponding sub echo estimator (22).

Claim 9

(9) An echo canceller according to claims from 1 - 7, wherein said step gains for coefficient updating in said main and corresponding sub echo estimators (21, 22) are chosen from prepared values through said convergence control processor (24) according to the situation of said sub echo estimator (22) determined by levels of at least said main and sub residual echoes.

Claim 10

(10) An echo canceller according to claims 1 - 9, wherein a double talk detector (13) and/or a low level detector ( 14) for said receive input signal are provided for controlling said step gains in said main echo estimators (21) and/or in said sub echo estimators (22).