Switch coupled between input and output ports in communication system

Claim 2

A switch as claimed in claim 1, characterized in that said output control means comprises: coder means (26₁-26 N , 27) for receiving said input acknowledgement signal from each of the memories and for generating the port number signal indicating one of the memories which has received data each time the input acknowledgement signal is received; and order control memory means (28), coupled between said coder means and said multiplexer means, for storing the port number signal generated each time the input acknowledgement signal is generated and outputting the port number signal to said multiplexer means by a first-in first-out process.

Claim 3

A switch as claimed in claim 1, characterized in that said output control means comprises: synchronizing means (29₁-29 1N ) for synchronizing input acknowledgement signals from the memories with each other and for outputting synchronized input acknowledgement signals; order control memory means (28), coupled to said synchronizing means, for storing the input acknowledgement signals and outputting the input acknowledgement signals by a first-in first-out process; and coder means (32), coupled between said order control memory means and said multiplexer means, for sequentially generating the port number signal indicating one of the memories each time the input acknowledgement signal is read out from said order control memory means.

Claim 4

A switch as claimed in claim 1, characterized in that said output control means comprises: coder means (26₁-26 N , 27) for receiving said input acknowledgement signal from each of the memories and for generating the port number signal indicating one of the memories which has received data each time the input acknowledgement signal is received; order control memory means (28), coupled between said coder means and said multiplexer means, for storing the port number signal generated each time the input acknowledgement signal is generated and outputting the port number signal to said multiplexer means by a first-in first-out process; counter means (33), coupled to said order control memory means, for generating a counter number which is incremented when there is no data in said order control memory means, said counter number serving as a port number signal; and selector means (34), coupled to said order control memory means, said counter means and said multiplexer, for outputting the port number signal from said order control memory means to said multiplexer means when said order control memory means stores the port number signal and for outputting the counter number from said counter means when there is no data in said order control memory means.

Claim 5

A switch as claimed in claim 1, characterized in that said output control means comprising: synchronizing means (29₁-29 N ) for synchronizing input acknowledgement signals from the memories with each other and for outputting synchronized input acknowledgement signals; order control memory means (28), coupled to said synchronizing means, for storing the input acknowledgement signals and outputting the input acknowledgement signals by a first-in first-out process; coder means (32), coupled between said order control memory means and said multiplexer means, for sequentially generating the port number signal indicating one of the memories each time the input acknowledgement signal is read out from said order control memory means; counter means (33), coupled to said order control memory means, for generating a counter number which is incremented when there is no data in said order control memory means, said counter number serving as a port number signal; and selector means (34), coupled to said order control memory means, said counter means and said multiplexer, for outputting the port number signal from said coder means to said multiplexer means when said order control memory means stores the port number signal and for outputting the counter number from said counter means when there is no data in said order control memory means.

Claim 6

A switch as claimed in claim 1, characterized in that said output control means comprises: coder means (26₁-26 N , 27) for receiving said input acknowledgement signal from each of the memories and for generating the port number signal indicating one of the memories which has received data each time the input acknowledgement signal is received; order control memory means (28), coupled between said coder means and said multiplexer means, for storing the port number signal generated each time the input acknowledgement signal is generated and outputting the port number signal to said multiplexer means by a first-in first-out process; and counter means (35), operatively coupled to said order control memory means, for generating a cyclic counter value which periodically indicates one of the input ports and for writing the cyclic counter value into said order control memory means, and in that said multiplexer means selects periodically one of the memories in response to said cyclic counter value.

Claim 7

A switch as claimed in claim 1, characterized in that said output control means comprising: synchronizing means (29₁-29 N ) for synchronizing input acknowledgement signals from the memories with each other and for outputting synchronized input acknowledgement signals; order control memory means (28), coupled to said synchronizing means, for storing the input acknowledgement signals and outputting the input acknowledgement signals by a first-in first-out process; coder means (32), coupled between said order control memory means and said multiplexer means, for sequentially generating the port number signal indicating one of the memories each time the input acknowledgement signal is read out from said order control memory means; counter means (35), coupled to said corder means, for generating a cyclic counter value which periodically indicates one of the input ports and for outputting the cyclic counter value to said coder means, and in that said multiplexer means selects periodically one of the memories in response to a port number signal derived from said cyclic counter value by said coder means.

Claim 8

A switch as claimed in claim 1, characterized in that said output control means comprises: coder means (26₁-26 N , 27) for receiving said input acknowledgement signal from each of the memories and for generating the port number signal indicating one of the memories which has received data each time the input acknowledgement signal is received; order control memory means (28), coupled between said coder means and said multiplexer means, for storing the port number signal generated each time the input acknowledgement signal is generated and outputting the port number signal to said multiplexer means by a first-in first-out process; first counter mesas (33), coupled to said order control memory means, for generating a first counter number which is incremented when there is no data in said order control memory means, said first counter number serving as a port number signal; selector means (34), coupled to said order control memory means, said first counter means and said multiplexer, for outputting the port number signal from said order control memory means to said multiplexer means when said order control memory means stores the port number signal and for outputting the first counter number from said counter means when there is no data in said order control memory means; and second counter means (35), operatively coupled to said order control memory means, for generating a second cyclic counter value which periodically indicates one of the input ports and for writing the second cyclic counter value into said order control memory means, and in that said multiplexer means selects periodically one of the memories in response to said cyclic value.

Claim 9

A switch as claimed in claim 1, characterized in that said output control means comprising: synchronizing means (29₁-29 N ) for synchronizing input acknowledgement signals from the memories with each other and for outputting synchronized input acknowledgement signals; order control memory means (28), coupled to said synchronizing means, for storing the input acknowledgement signals and outputting the input acknowledgement signals by a first-in first-out process; coder means (32), coupled between said order control memory means and said multiplexer means, for sequentially generating the port number signal indicating one of the memories each time the input acknowledgement signal is read out from said order control memory means; first counter means (33), coupled to said order control memory means, for generating a first counter number which is incremented when there is no data in said order control memory means, said first counter number serving as a port number signal; selector means (34), coupled to said order control memory means, said first counter means and said multiplexer, for outputting the port number signal from said coder means to said multiplexer means when said order control memory means stores the port number signal and for outputting the first counter number from said counter means when there is no data in said order control memory means; second counter means (35), coupled to said corder means, for generating a second cyclic counter value which periodically indicates one of the input ports and for outputting the second cyclic counter value to said coder means, and in that said multiplexer means selects periodically one of the memories in response to a port number signal derived from said second cyclic counter value by said coder means.