Patent EP0503514A2 successfully refreshed from Google Patents.
EP0503514A2
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EP
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Backward-compatible computer architecture with extended word size and address space
Assignee: MIPS Tech LLC
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Filing: 1992-03-07
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Granted: —
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Expires: 2012-03-07
Abstract
Abstract A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended versions of m-bit entities, produce an N-bit result that may not correspond to the correct m-bit result, sign-extended to N bits. For these instructions compatibility requires that the instructions be further defined to guarantee a sign-extended result. This means that separate N-bit instructions corresponding to these m-bit instructions are needed. The support for up to an N-bit virtual address space is provided in part by widening the virtual address data paths. The extended architecture supports the m-bit architecture's addressing with minimal additional hardware. This is made possible by storing m-bit addresses as N-bit entities in sign-extended form and requiring that the results of address computations on these entities be in sign-extended form.
Inventors
- 👤 Earl A. Killian
- 👤 Thomas J. Riordan
- 👤 Danny L. Freitas
- 👤 Ashish B. Dixit
- 👤 John L. Hennessy
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 13:13
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30036; G06F9/30038; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/30181; G06F9/30189; G06F9/30192; G06F9/32; G06F9/322; G06F9/324
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
362 words
In a computer system including a processing unit and a memory subsystem, a processing unit comprising: means, responsive to instructions fetched from the memory subsystem, for specifying corresponding operations; a first subset of instructions, called m-bit instructions, including a number of m-bit load instructions, a number of logical operation instructions, a number of m-bit shift instructions, and a number of m-bit addition instructions, and a second subset of instructions, called N-bit instructions, including a number of N-bit load instructions, a number of N-bit shift instructions, and a number of N-bit addition instructions; a load circuit for performing designated load operations to retrieve entities up to N bits long from the memory subsystem; load sign-extend means, controllably operable to sign-extend to N bits a retrieved entity of m bits; a register file having a set of N-bit registers; a logic circuit for performing specified logical operations between two N-bit operands; a shift circuit for performing specified shift operations on an N-bit operand; shift sign-extend means, controllably operable to sign-extend the result of a shift operation from m to N bits; an adder for performing specified addition operations between a pair of N-bit operands; add sign-extend means, controllably operable to sign-extend the result of an operation in said adder from m to N bits; means for detecting m-bit overflow in said adder; means defining N-bit data paths from output ports of each of said load circuit, said logic circuit, said shift circuit, and said adder to said register file; means for defining N-bit data paths from said register file to input ports of each of said logic circuit, said shift circuit, and said adder; means for activating said load sign-extend means in response to at least one m-bit load instruction; means for activating said shift sign-extend means in response to at least one m-bit shift instruction; and means for activating said add sign-extend means in response to at least one m-bit addition instruction and the occurrence of an m-bit overflow; said means for activating said load sign-extend means, said means for activating said shift sign-extend means, and said means for activating said add sign-extend means being non-responsive to N-bit load, shift, and addition instructions.
Claim 2
Dependent Claim
10 words
The processing unit of claim 1 wherein N=64 and m=32.
Claim 3
Dependent Claim
44 words
The processing unit of claim 1, and further comprising means, associated with said load circuit and said load sign-extend means, for sign-extending or zero-extending to m bits a retrieved entity of fewer than m bits to further define a retrieved entity of m bits.
Claim 4
Dependent Claim
25 words
The processing unit of claim 1 wherein said means for activating said add sign-extend means is responsive only in the event of an m-bit overflow.
Claim 5
Dependent Claim
71 words
The processing unit of claim 1 wherein said m-bit addition instructions include ADD and SUB instructions that trap on an m-bit overflow and produce no result, and ADDU and SUBU instructions that do not trap on an m-bit overflow and do produce a result, and wherein said means for activating said add sign-extend means is responsive to said ADDU and SUBU instructions and is non-responsive to said ADD and SUB instructions.
Claim 6
Dependent Claim
56 words
The processing unit of claim 1, and further comprising means for detecting N-bit overflow in said adder, and wherein said N-bit addition instructions include DADD and DSUB instructions that trap on an N-bit overflow and produce no result, and DADDU and DSUBU instructions that do not trap on an N-bit overflow and do produce a result.
Claim 7
Dependent Claim
114 words
In the execution unit of a data processor, an adder operable to combine two N-bit operands, with the most significant bit being designated bit(N-1) and the least significant bit being designated bit(0), comprising: means, responsive to a first opcode, designated an N-bit add, for adding a pair of input operands and providing the result of the addition; and means, responsive to a second opcode, designated an m-bit add, for adding a pair of input operands and, for at least those cases where bit(m) of the initial result is unequal to bit(m-1) of the initial result, for setting bit(N-1) through bit(m) to the value of bit(m-1) of the initial result, prior to presenting the result.
Claim 8
Dependent Claim
123 words
In the execution unit of a data processor, a shift unit operable to shift an N-bit operand, with the most significant bit being designated bit(N-1) and the least significant bit being designated bit(0), comprising: means, responsive to a first opcode, designated an N-bit logical right shift, for shifting an input operand a designated number of bit positions to the right and, if the designated number is non-zero, filling the vacated bit positions with 0's; and means, responsive to a second opcode, designated an m-bit logical right shift, for shifting an input operand a designated number of bit positions to the right and, if the designated number is non-zero, filling the vacated bit positions and the next N-m most significant bit positions with 0's.
Claim 9
Dependent Claim
134 words
In the execution unit of a data processor, a shift unit operable to shift an N-bit operand, with the most significant bit being designated bit(N-1) and the least significant bit being designated bit(0), comprising: means, responsive to a first opcode, designated an N-bit left shift, for (1) shifting an input operand a designated number of bit positions to the left and, if the designated number is non-zero, (2) filling the vacated bit positions with 0's; and means, responsive to a second opcode, designated an m-bit left shift, for (1) shifting an input operand a designated number of bit positions to the left and, if the designated number is non-zero, (2) filling the vacated bit positions with 0's, and (3) setting bit(N-1) through bit(m) of the result to the value of bit(m-1) of the result.
Claim 10
Dependent Claim
286 words
A computer having registers and data paths that are N bits wide and being capable of supporting an extended architecture defined for N-bit data entities, being backward compatible with an architecture defined for m-bit data entities (where m is less than N) and having a set of instructions, called m-bit instructions, the computer being characterized in that: a first subset of the m-bit instructions, when redefined to operate on N-bit entities without other modification, inherently operate on N-bit sign-extended entities to produce a result that is sign-extended; a second subset of the m-bit instructions, when redefined to operate on N-bit entities without other modification, operate on N-bit sign-extended entities to produce a result that is not necessarily sign-extended; a third subset of the m-bit instructions are load instructions that load data entities of fewer than m bits, and perform an extension of the entities to m bits; a first subset of the extended architecture instruction set includes the first subset of m-bit instructions, redefined to operate on N-bit entities without other modification; a second subset of the extended architecture instruction set includes the second subset of m-bit instructions, redefined to operate on N-bit entities and further defined to ensure that bit(N-1) through bit(m) are equal to the value of bit(m-1); a third subset of the extended architecture instruction set includes the third subset of m-bit instructions, redefined to load data entities of fewer than m bits, and perform the same type of extension to N bits as the third subset of m-bit instructions perform to m bits; a fourth subset of the extended architecture instruction set includes at least some of the second subset of m-bit instructions, redefined to operate on N-bit entities without other modification.
Claim 11
Dependent Claim
71 words
The computer of claim 10, being further characterized in that: the first subset of the extended architecture instruction set includes logical operation instructions, set instructions, and branch instructions; the second subset of the extended architecture instruction set includes addition and subtraction instructions, multiplication and division instructions, and shift instructions; and the fourth subset of the extended architecture instruction set includes addition and subtraction instructions, multiplication and division instructions, and shift instructions.
Claim 12
Dependent Claim
215 words
A computer having an address unit with data paths that are N bits wide and being capable of supporting an extended architecture with an N-bit virtual address field, the computer being backward compatible with a prior architecture with an m-bit virtual address field, where m is less than N, the prior architecture having a virtual address map wherein kernel and user addresses are distinguished by the value of bit(m-1) of the m-bit virtual address, the computer being characterized in that: the R most significant bits of the N-bit virtual address define a plurality of regions including a bottom region starting at address 0 and a top region ending at address 2 N -1; the extended architecture has a virtual address map that includes a 2 VSIZE -byte user space starting at the bottom of the bottom region, a first kernel space starting at the bottom of one of the regions other than the bottom region, and a second kernel space ending at the top of the top region, the second kernel space being the same size as the prior architecture's kernel space, 2 VSIZE being greater than the size of the prior architecture's user space but smaller than the size of a region; and the computer includes means for sign-extending m-bit addresses to N bits.
Claim 13
Dependent Claim
11 words
The computer of claim 12 wherein VSIZE is greater than m.
Claim 14
Dependent Claim
18 words
The computer of claim 12 wherein the first kernel space starts at the bottom of the top region.
Claim 15
Dependent Claim
166 words
In a computer system, address logic comprising: means for generating an N-bit virtual address (VA) with bits being designated VA(N-1) for the most significant bit and VA(0) for the least significant bit, with the R most significant VA bits defining a plurality of regions; address translation means, responsive to at least a portion of the VA, for generating a physical address on the basis of the VA bits to which it is responsive; a TLB associated with said address translation means, responsive to at least some of the R most significant VA bits and to a range of VA bits including VA(VSIZE-1) and bits less significant than VA(VSIZE-1), where VSIZE is less than or equal to (N-R), and non-responsive to VA(N-R-1) through VA(VSIZE), for generating a mapped physical address; means, responsive to at least some of the R most significant VA bits and to VA(N-R-1) through VA(VSIZE), for generating an error signal if for at least one particular region VA(N-R-1) through VA(VSIZE) are not all 0's.
Claim 16
Dependent Claim
45 words
The address logic of claim 15 wherein said address translation means includes means, responsive to at least some VA bits defining a range of unmapped addresses, for generating an unmapped physical address having bits taken directly from VA bits without being translated by said TLB.
Claim 17
Dependent Claim
93 words
The address logic of claim 15 wherein: the computer may be in a selected one of a plurality of modes including a user mode and a kernel mode; one of said plurality of regions is designated the user region; said address error means specifies an address error when the computer is in user mode and the R most significant VA bits specify a region other than the user region; and said address error means specifies no address error for at least one address in every region when the computer is in kernel mode.
Claim 18
Dependent Claim
32 words
The address logic of claim 15 wherein the range of permitted addresses in kernel mode includes addresses having VA(N-1) through VA(m-1) all 1's, where m is less than or equal to VSIZE.
Claim 19
Dependent Claim
296 words
In a computer system capable of supporting an extended architecture characterized by an N-bit virtual address (VA) field containing bits VA(N-1) through VA(0), the computer being backward compatible with a prior architecture characterized by an m-bit VA field containing bits VA(m-1) through VA(0), where m is less than N, address logic comprising: address translation means, responsive to a first high order set of VA bits in the range between VA(N-1) and VA(m) and a first low order set of VA bits in the range between VA(m) and VA(0), for generating a physical address on the basis of the VA bits to which it is responsive; address error means, responsive to a second high order set of VA bits in the range between VA(N-1) and VA(m) and a second low order set of VA bits in the range between VA(m-1) and VA(0), for generating an address error if the VA is in a range defined to be unavailable; the first and second high order sets having respective first and second numbers of bits therein; means, responsive to an N-bit VA, for communicating the first high order and low order sets of bits of the N-bit VA to the address translation means, and for communicating the second high order and low order sets of bits of the N-bit VA to the address error means; and means, responsive to an m-bit VA, for communicating the value of VA(m-1) of the m-bit VA, replicated the first number of times, and the first low order set of bits of the m-bit VA to the address translation means, and for communicating the value of VA(m-1) of the m-bit VA, replicated the second number of times, and the second low order set of bits of the m-bit VA to the address error means.
Claim 20
Dependent Claim
24 words
The address logic of claim 19 wherein the first set comprises fewer than all the VA bits in the range between VA(N-1) and VA(m).
Claim 21
Dependent Claim
22 words
The address logic of claim 19 wherein the second set comprises all the VA bits in the range between VA(m-1) and VA(0).
Claim 22
Dependent Claim
22 words
The address logic of claim 19 wherein the third set comprises all the VA bits in the range between VA(N-1) and VA(m).
Claim 23
Dependent Claim
24 words
The address logic of claim 19 wherein the fourth set comprises fewer than all the VA bits in the range between VA(m-1) and VA(0).
References Cited (Backward Citations)
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