Semiconductor device having an interconnecting circuit board and method for manufacturing same

Claim 2

A semiconductor device according to claim 1, wherein the number of electrically connecting electrode pads (22) is greater than the number of inner leads (25).

Claim 3

A semiconductor device, comprising: an island (30) formed in a predetermined plane; a semiconductor chip (31) having a plurality of electrically connecting electrode pads (32), the chip (31) being disposed on the island (30); and a plurality of inner leads (34) disposed around the island (30); characterized by an interconnecting circuit board (33) having an electrically conductive pattern (37), the circuit board (33) being disposed on the plurality of inner leads (34) and surrounding the semiconductor chip (31); a first electrically connecting means (36c) for connecting the electrically conductive pattern (37) and one (32b) of the electrically connecting electrode pads (32); and a second electrically connecting means (36b) for connecting the electrically conductive pattern (37) and one (34a) of the inner leads (34).

Claim 4

A semiconductor device according to claim 3, wherein the number of electrically connecting electrode pads (32) is greater than the number of inner leads (34).

Claim 5

A semiconductor device according to claim 3, wherein the interconnecting circuit board (33) partially surrounds the semiconductor chip (31).

Claim 6

A semiconductor device, comprising: an island (40) formed in a predetermined plane; a semiconductor chip (41) having a plurality of electrically connecting electrode pads (42), the chip (41) being disposed on the island (40); and a plurality of inner leads (45) disposed around the island (40) and the semiconductor chip (41); characterized by a first interconnecting circuit board (43) having a first electrically conductive pattern (47), the first interconnecting circuit board (43) being disposed on the semiconductor chip (41); a first electrically connecting means (46a,46b) for connecting the first electrically conductive pattern (47) and a first one of the inner leads (45); a second electrically connecting means (46c) for connecting the first electrically conductive pattern (47) and a first one (42b) of the electrically connecting electrode pads (42); a second interconnecting circuit board (49) having a second electrically conductive pattern (50), the second interconnecting circuit board (49) being disposed on the plurality of the inner leads (45); a third electrically connecting means (46e) for connecting the second electrically conductive pattern (50) and a second one (42c) of the electrically connecting electrode pads (42); and a fourth electrically connecting means (46d) for connecting the second electrically conductive pattern (50) and a second one (45b) of the inner leads (45).

Claim 7

A semiconductor device according to claim 6, wherein the number of electrically connecting electrode pads (42) is greater than the number of inner leads (45).

Claim 8

A semiconductor device having an interconnecting circuit board, the device comprising: an island (60) formed in a predetermined plane; a first semiconductor chip (61) having a plurality of electrically connecting electrode pads (62), the first chip (61) being disposed on the island (60); a second semiconductor chip (66) having a plurality of electrically connecting electrode pads (67), the second chip (66) being disposed on the island (60); an electric connecting circuit board (71) having a plurality of electrically connecting electrode pads (72) and a third electrically conductive pattern (73) connected to the electrically connecting electrode pads (72), the electric connecting circuit board (71) being disposed on the island (60) and between the first semiconductor chip (61) and the second semiconductor chip (66); and a plurality of inner leads (74) disposed around the island (60); characterized by a first interconnecting circuit board (63) having a first electrically conductive pattern (64) and a plurality of electrically connecting electrode pads (65) connected to the first electrically conductive pattern (64), the first interconnecting circuit board (63) being disposed on the first semiconductor chip (61); a second interconnecting circuit board (68) having a second electrically conductive pattern (69) and a plurality of electrically connecting electrode pads (70a,70b) electrically connected to the second electrically conductive pattern (69), the second interconnecting circuit board (68) being disposed on the second semiconductor chip (66); a first electrically connecting means (75a) for connecting a first one (74a) of the inner leads (74) and a first one (62a) of the electrically connecting electrode pads (62) on the first semiconductor chip (61); a second electrically connecting means (75b) for connecting a second one (74b) of the inner leads (74) and a first one (65a) of the electrically connecting electrode pads (65) on the first interconnecting circuit board (63); a third electrically connecting means (75c) for connecting a third one (74c) of the inner leads (74) and a first one (72a) of the electrically connecting electrode pads (72) on the electric connecting circuit board (71); a fourth electrically connecting means (75d) for connecting a second one (62b) of the electrically connecting electrode pads (62) on the first semiconductor chip (61) and a second (75d) one of the electrically connecting electrode pads (72) on the electric connecting circuit board (71); a fifth electrically connecting means (75e) for connecting a second one (65b) of the electrically connecting electrode pads (65) on the first interconnecting circuit board (63) and a third one (72c) of the electric connecting electrode pads (72) on the electric connecting circuit board (71); a sixth electrically connecting means (75f) for connecting the fourth electrically connecting electrode pad (72d) on the electrically connecting circuit board (71) and a first one (67a) of the electrically connecting electrode pads (67) on the second chip (66); a seventh electrically connecting means (75g) for connecting a fifth one (72e) of the electrically connecting electrode pads (72) on the electric connecting circuit board (71) and a first one (70a) of the electrically connecting electrode pads (70a,70b) on the second interconnecting circuit board (68); an eighth electrically connecting means (75h) for connecting a second one (70b) of the electrically connecting electrode pads (70a,70b) on the second interconnecting circuit board (68) and a second one (67b) of the electrically connecting electrode pads (67) on the second chip (66); and a ninth electrically connecting means (75i) for connecting a third one (67c) of the electrically connecting electrode pads (67) on the second chip (66) and a fourth one (74d) of the inner leads (74).

Claim 9

A semiconductor device, comprising: an island (60) formed in a predetermined plane; a first semiconductor chip (63) having a plurality of electrically connecting electrode pads (65), the first chip (61) being disposed on the island (60); a second semiconductor chip (66) having a plurality of electrically connecting electrode pads (67), the second chip (66) being disposed on the island (60); an electric connecting circuit board (71) having a plurality of electrically connecting electrode pads (72) and an electrically conductive pattern (73) connected to the electrically connecting electrode pads (72), which is disposed on the island (60) and between the first semiconductor chip (61) and the second semiconductor chip (66); and a plurality of inner leads (74) disposed around the island (60); characterized by an interconnecting circuit board (80) disposed on the inner leads (74) and having an electrically conductive pattern (81); a first electrically connecting means (75j) for connecting a first one (74e) of the inner leads (74) and the electrically conductive pattern (81) of the interconnecting circuit board (80); a second electrically connecting means (75a) for connecting a second one (74a) of inner leads (74) and a first one (62a) of electrically connecting electrode pads (62) on the first chip (61); a third electrically connecting means (75c) for connecting a third one (74c) of the inner leads (74) and a first one (72a) of the electrically connecting electrode pads (72) on the circuit board (71); a fourth electrically connecting means (75d) for connecting a second one (72b) of the electrically connecting electrode pads (72) on the circuit board (71) and a second one (62b) of the electrically connecting electrode pads (62) on the first chip (61); a fifth electrically connecting means (75f) for connecting a third one (72d) of the electrically connecting electrode pads (72) on the circuit board (71) and a first one (67a) of the electrically connecting electrode pads (67) on the second chip (66); a sixth electrically connecting means (75i) for connecting a second one (67c) of the electrically connecting electrode pads (67) on the second chip (66) and a fourth one (74d) of the inner leads (74); and a seventh electrically connecting means (75k) for connecting a third one (67d) of the electrically connecting electrodes (67) on the second chip (66) and the electrically conductive pattern (81) on the interconnecting circuit board (80).

Claim 10

A semiconductor device, comprising: an island (60) formed in a predetermined plane; a first semiconductor chip (61) having a plurality of electrically connecting electrode pads (62), the first chip (61) being disposed on the island (60); a second semiconductor chip (66) having a plurality of electrically connecting electrode pads (67), the second chip (66) being disposed on the island (60); an electric connecting circuit board (71) having a plurality of electrically connecting electrode pads (72) and an electrically conductive pattern (73) connected to the electrically connecting electrode pads (72), the electric connecting circuit board (71) being disposed on the island (60) and between the first semiconductor chip (61) and the second semiconductor chip (66); and a plurality of inner leads (74) disposed around the island (60); characterized by a first interconnecting circuit board (63) having a electrically conductive pattern (64) and a plurality of electrically connecting electrode pads (65) connected to the electrically conductive pattern (64), the first interconnecting circuit board (63) being disposed on the first semiconductor chip (61): a second interconnecting circuit board (68) having an electrically conductive pattern (69) and a plurality of electrically connecting electrode pads (70a,70b) connected to the electrically conductive pattern (69), the second interconnecting circuit board (68) being disposed on the second semiconductor chip (66); a third interconnecting circuit board (80) having a electrically conductive pattern (81) on the inner leads (74); a first electrically connecting means (75a) for connecting a first one (74a) of the inner leads (74) and a first one (62a) of the electrically connecting electrode pads (62) on the first chip (61); a second electrically connecting means (75j) for connecting a second one (74e) of the inner leads (74) and the electrically conductive pattern (81) on the third interconnecting circuit board (80); a third electrically connecting means (75b) for connecting a third one (74b) of the inner leads (74) and a first one (65a) of the electrically connecting electrode pads (65) on the first interconnecting circuit board (63); a fourth electrically connecting means (75n) for connecting a second one of the electrically connecting electrode pads (62) on the first chip (61) and a second electrically connecting electrode pads (65) on the first interconnecting circuit board (63); a fifth electrically connecting means (75c) for connecting a fourth one (74c) of the inner leads (74) and a first one (72a) of the electrically connecting electrode pads (72) on the electric connecting circuit board (71); a sixth electrically connecting means (75d) for connecting a third one (62b) of the electrically connecting electrode pads (62) on the first chip (61) and a second one (72b) of the electrically connecting electrode pads (72) on the electric connecting circuit board (71); a seventh electrically connecting means (75e) for connecting a third one (65b) of the electrically connecting electrode pads (65) on the first interconnecting circuit board (63) and a third one (72c) of the electrically connecting electrode pads (72) on the electric connecting circuit board (71); an eighth electrically connecting means (75f) for connecting a fourth one (72d) of the electrode pads (72) on the electric connecting circuit board (71) and a first one (67a) of the electrically connecting electrode pads (67) on the second chip (66); a ninth electrically connecting means (75g) for connecting a fifth one (72e) of the electrically connecting electrode pads (72) on the electric connecting circuit board (71) and a first one (70a) of the electrically connecting electrode pads (70a,70b) on the second interconnecting circuit board (68); a tenth electrically connecting means (75h) for connecting a second one (70b) of the electrically connecting electrode pads (70a,70b) on the second interconnecting circuit board (68) and one (67b) of the electrically connecting electrode pads (67) on the second chip (66); an eleventh electrically connecting means (75i) for connecting the third one (67c) of the electrically connecting electrode pads (67) on the second chip (66) and the fifth one (74d) of the inner leads (74); and a twelfth electrically connecting means (75k) for connecting the fourth one (67d) of the electrically connecting electrode pads (67) on the second chip (66) and the electrically conductive pattern (81) on the third interconnecting circuit board (80).

Claim 11

A semiconductor device having an interconnecting circuit board according to claims 1, 3, 6, 8, 9, or 10 wherein the electric connecting means (26a,26b,36c,36b,46a,46b,46c,46d,75a,75b,75c, 75d,75e,75f,75h,75i,75j,75k) are formed of copper, the electric connecting electrode pads (22,32,42,62,65,67,70a,70b,72) are formed from material selected from material selected from the group consisting of nickel, copper, and gold, and the interconnecting circuit boards (23,33,43,49,63,68,80) are formed from material selected from the group consisting of glass epoxy resin and polyimide.

Claim 12

A semiconductor device according to claim 6 or 10, wherein the interconnecting circuit board (49,80) on the inner leads (45,74) and the interconnecting circuit board (43,63,68) on the semiconductor chip (41,61,66) comprise an integrally formed unitary structure and are coplanar.

Claim 13

A semiconductor device having an interconnecting circuit board according to claim 6 or 10, wherein the interconnecting circuit board (43,63,68) on the chip (41,61,66) and the interconnecting circuit board (49,80) on the inner leads (45,74) comprise an integrally formed unitary structure, and wherein the semiconductor device further comprises means (110), passing under the interconnecting circuit board (49,80) on the inner leads (45,74), for electrically connecting electrode pads on the chip (41,61,66) and the inner leads (45,74).

Claim 14

A semiconductor device having an interconnecting circuit board according to claim 6 or 10, wherein the interconnecting circuit board (43,63,68) on the chip (41,61,66) and the interconnecting circuit board (49,80) on the inner leads (45,74) comprise an integrally formed unitary structure, and wherein the semiconductor device comprises means (150), passing over the interconnecting circuit board (49,80) on the inner leads (45,74), for electrically connecting electrode pads (42,62,67) on the chip (41,61,66) and the inner leads (45,74).

Claim 15

A semiconductor device according to claim 1, 6, 8, 9, or 10 wherein the island (20,30,40,60) is depressed from the inner leads (25,34,45,74), and the plane of the island (20,30,40,60) is formed at a lower level than that of the inner leads (25,34,45,74).

Claim 17

A semiconductor device, comprising: an island (20); a semiconductor chip (21) having a plurality of electrically connecting electrode pads (22), the chip (21) being disposed on the island (20); and a plurality of inner leads (25) disposed around the island (20); characterized by an interconnecting circuit board (23) having an electrically conductive pattern (27), the interconnecting circuit board (23) being disposed on the semiconductor chip (21); and means (26) providing selective electrical interconnection between the chip (21), the interconnecting circuit board (23), and the plurality of inner leads (25).

Claim 18

A semiconductor device according to claim 18, wherein the number of electrically connecting electrode pads (22) is greater than the number of inner leads (25).

Claim 19

A semiconductor device, comprising: an island (20); a semiconductor chip (31) disposed on the island (30); and a plurality of inner leads (34) disposed around the island (30); characterized by an interconnecting circuit board (33) having an electrically conductive pattern (37), the circuit board (33) being disposed on the plurality of inner leads (34) and surrounding the semiconductor chip (31); and means (36) for providing selective electrical interconnection between the chip (31), the interconnecting circuit board (33), and the plurality of inner leads (34).

Claim 20

A semiconductor device, comprising: an island (40); a semiconductor chip (41) disposed on the island (40); and a plurality of inner leads (45) disposed around the island (40) and the semiconductor chip (41); characterized by a first interconnecting circuit board (43) having a first electrically conductive pattern (47), the first interconnecting circuit board (43) being disposed on the semiconductor chip (41); a second interconnecting circuit board (49) having a second electrically conductive pattern (50), the second interconnecting circuit board (49) being disposed on the plurality of the inner leads (45); means (46) for providing selective electrical interconnection between the chip (41), the first and second interconnecting circuit boards (43,49), and the plurality of inner leads (45).

Claim 21

A semiconductor device having an interconnecting circuit board according to claim 21, wherein: the first and second interconnecting circuit boards (43,49) comprise an integrally formed unitary structure; and the means (46) for providing selective electrical interconnection comprises means (110), passing under the second interconnecting circuit board (49), for electrically connecting the chip (41) and the inner leads (45).

Claim 22

A semiconductor device having an interconnecting circuit board according to claim 21, wherein: the first and second interconnecting circuit boards (43,49) comprise an integrally formed unitary structure; and the means (46) for providing selective electrical interconnection comprises means (150), passing over the second interconnecting circuit board, for electrically connecting the chip (41) and the inner leads (45).

Claim 23

A semiconductor device, comprising: an island (60); a first semiconductor chip (61) disposed on the islands (60); a second semiconductor chip (66) disposed on the island (60); an electric connecting circuit board (71) having an electrically conductive pattern (73), the electric connecting circuit board (71) being disposed on the island (60) and between the first semiconductor chip (61) and the second semiconductor chip (66); and a plurality of inner leads (74) disposed around the island (60); characterized by a first interconnecting circuit board (63) having an electrically conductive pattern (64), the first interconnecting circuit board (63) being disposed on the first semiconductor chip (61); a second interconnecting circuit board (68) having an electrically conductive pattern (69), the second interconnecting circuit board (68) being disposed on the second semiconductor chip (66); and means (75) for providing selective electrical interconnection between the first and second chips (61,66), the first and second interconnecting circuit boards (63,68), the electric connecting circuit board (71), and the plurality of inner leads (74).

Claim 24

A semiconductor device, comprising: an island (60); a first semiconductor chip (61) disposed on the island (60); a second semiconductor chip (66) disposed on the island (60); an electric connecting circuit board (71) having an electrically conductive pattern (73), the electric connecting circuit board (71) being disposed on the island (60) and between the first semiconductor chip (61) and the second semiconductor chip (66); and a plurality of inner leads (74) disposed around the island (60); characterized by an interconnecting circuit board (80) disposed on the inner leads (74) and having an electrically conductive pattern (81); and means (75) for providing selective electrical interconnection between the first and second chips (61,66), the interconnecting circuit board (80), the electric connecting circuit board (71), and the plurality of inner leads (74).

Claim 25

A semiconductor device, comprising: an island (60); a first semiconductor chip (61) disposed on the island (60); a second semiconductor chip (66) disposed on the island (60); an electric connecting circuit board (71) having an electrically conductive pattern (73) connected to the electrically connecting electrode pads (72), the electric connecting circuit board (71) being disposed on the island (60) and between the first semiconductor chip (61) and the second semiconductor chip (66); and a plurality of inner leads (74) disposed around the island (60); characterized by a first interconnecting circuit board (63) having a electrically conductive pattern (64), the first interconnecting circuit board (63) being disposed on the first semiconductor chip (61); a second interconnecting circuit board (68) having an electrically conductive pattern (69), the second interconnecting circuit board (68) being disposed on the second semiconductor chip (66); a third interconnecting circuit board (80) having a electrically conductive pattern (81) on the inner leads (74); and means (75) for providing selective electrical interconnection between the first and second chips (61,66), the first, second, and third interconnecting circuit boards (63,68,80), the electric connecting circuit board (71), and the plurality of inner leads (74).

Claim 26

A semiconductor device according to claim 26, wherein, the first, second, and third interconnecting circuit boards (63,68,80) comprise an integrally formed unitary structure; and the means (75) for providing selective electrical interconnection comprises means (110), passing under the third interconnecting circuit board (80), for electrically connecting the chips (61,66) and the inner leads (74).

Claim 27

A semiconductor device according to claim 26, wherein: the first, second, and third interconnecting circuit boards (63,68,80) comprise an integrally formed unitary structure; and the means (75) for providing selective electrical interconnection comprises means (150), passing over the third interconnecting circuit board (80), for electrically connecting the chips (61,66) and the inner leads (74).

Claim 28

A semiconductor device, comprising: an island (60); a first semiconductor chip (61) disposed on the island (60); a second semiconductor chip (66) disposed on the island (60); and a plurality of inner leads (74) disposed around the island (60); characterized by an interconnecting circuit board (80) disposed on the inner leads (74) and having an electrically conductive pattern (81); and means (75) for providing selective electrical interconnection between the first and second chips (61,66), the interconnecting circuit board (80), and the plurality of inner leads (74).

Claim 29

A semiconductor device, comprising: an island (60); a first semiconductor chip (61) disposed on the island (60); a second semiconductor chip (66) disposed on the island (60); and a plurality of inner leads (74) disposed around the island (60); a first interconnecting circuit board (63) having an electrically conductive pattern (64), the first interconnecting circuit board (63) being disposed on the first semiconductor chip (61); a second interconnecting circuit board (68) having an electrically conductive pattern (69), the second interconnecting circuit board (68) being disposed on the second semiconductor chip (66); and means (75) for providing selective electrical interconnection between the first and second chips (61,66), the first and second interconnecting circuit boards (63,68), and the plurality of inner leads (74).

Claim 30

A semiconductor device, comprising: an island (60); a first semiconductor chip (61) disposed on the island (60); a second semiconductor chip (66) disposed on the island (60); and a plurality of inner leads (74) disposed around the island (60); an interconnecting circuit board (80) disposed on the inner leads (74) and having an electrically conductive pattern (81); and means (75) for providing selective electrical interconnection between the first and second chips (61,66), the interconnecting circuit board (80),and the plurality of inner leads (74).