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EP0499460A2
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Semiconductor memory device
Assignee: Sharp Corp
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Filing: 1992-02-13
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Granted: —
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Expires: 2012-02-13
Abstract
Abstract In a semiconductor memory device, two sense amplifiers are provided on one output signal line for reading data stored in a memory cell. The sense amplifiers are connected in parallel to each other. A control signal generation circuit generates a control signal so that one of the sense amplifiers which has a greater drive capability is activated during a predetermined time period after an address from which data is to be read out is changed, and that the sense amplifier having a smaller drive capability is activated during a time period other than the predetermined time period. <IMAGE>
Inventors
- 👤 Yashuhiro Hotta
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 10:14
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C7/00; G11C7/06
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
53 words
A semiconductor memory device comprising: a plurality of sense amplifiers provided on one output signal line for reading data stored in a memory cell, said sense amplifiers being connected in parallel to each other; and a control signal generation circuit for generating a control signal by which said sense amplifiers are selectively activated.
Claim 2
Dependent Claim
33 words
A semiconductor memory device according to claim 1, wherein the drive capability of at least one of said sense amplifiers is greater than that of at least one other of said sense amplifiers.
Claim 3
Dependent Claim
73 words
A semiconductor memory device according to claim 2, wherein said control signal generation circuit generates said control signal so that said at least one sense amplifier having a greater drive capability is activated during a predetermined time period after an address from which a data is to be read out is changed, and that said at least one other sense amplifier is activated during a time period other than said predetermined time period.
Claim 4
Dependent Claim
17 words
A semiconductor memory device according to claim 1, wherein said sense amplifiers are differential type sense amplifiers.
Claim 5
Dependent Claim
67 words
A semiconductor memory device comprising: a control means (9), a memory cell output signal means (3), and amplifying means (6) for amplifying a memory cell output signal under the control of said control means (9), characterised in that said amplifying means (6) comprises a plurality of sense amplifiers (6a, 6b) connected in parallel with each other and adapted to be selectively activated by said control means (9).
Claim 6
Dependent Claim
36 words
A semiconductor memory device as claimed in claim 5, wherein at least one of said sense amplifiers is adapted to operate at a greater speed than that of at least one other of said sense amplifiers.
Claim 7
Dependent Claim
76 words
A semiconductor memory device as claimed in claim 6, wherein said control means is adapted to control said sense amplifiers such that said at least one sense amplifier adapted to operate at a greater speed is activated during a predetermined time period after an address from which data is to be read out is changed, and such that at least one other sense amplifier is activated during a time period other than said predetermined time period.
References Cited (Backward Citations)
No citation records indexed.
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