Patent EP0499383A2 successfully refreshed from Google Patents.
EP0499383A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Mixed mode analog/digital programmable interconnect architecture
Assignee: Microsemi SoC Corp
•
Filing: 1992-01-29
•
Granted: —
•
Expires: 2012-01-29
Abstract
Abstract A user-programmable integrated circuit includes an analog portion containing user-configurable analog circuit modules, a digital portion containing user-configurable digital circuit modules, an interface portion containing user-configurable interface circuits for conversion of signals from analog to digital form and from digital to analog form, and a user-configurable interconnection and input/output architecture.
Inventors
- 👤 Khaled A. El Ayat
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 10:04
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/002; G; G06; G06J; G06J1/00; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
531 words
An user-configurable integrated circuit architecture, including: a plurality of user-configurable digital logic circuit modules, each of said digital logic module having a plurality of inputs and at least one output, at least one of said digital logic circuit modules including means for configuring said digital logic module by a user to perform one of a plurality of functions; a plurality of user-configurable analog circuit modules, each of said analog circuit modules having an input and an output, at least one of said analog circuit modules including programmable means, programmable by a user, for selecting one or more circuit parameters for said at least one of said analog circuit modules; a first group of input/output pads on said integrated circuit, each one of said first group of input output pads communicating with the input of one of said analog circuit modules; a second group of input/output pads on said integrated circuit, each one of said second group of input/output pads communicating with the output of one of said analog circuit modules; at least one analog-to-digital converter having an analog input and a multibit digital output; at least one digital-to-analog converter having a multibit digital input and an analog output; a plurality of user configurable analog switches, first ones of said plurality of analog switches connected between ones of said input/output pads in said first group and the inputs of selected ones of said analog circuit modules, second ones of said analog switches connected between ones of said input/output pads in said second group and the outputs of selected ones of said analog circuit modules, second ones of said analog switches, third ones of said analog switches connected between the outputs of ones of said analog circuit modules and the analog input of said at least one analog-to-digital converter, fourth ones of said analog switches connected between the analog output of said at least one analog-to-digital converter and selected ones of said analog circuit modules and said input/output pads of said second group; a plurality of interconnect conductors associated with said plurality of digital logic circuit modules, the multibit digital output of said at least one analog-to-digital converter and the multibit digital input of said at least one digital-to-analog converter, each of said interconnect conductors divided into one or more segments, at least some first ones of said segments running in a first direction and at least some second ones of said segments running in a second direction different from said first direction so as to form intersections between said first ones and second ones of said segments; a plurality of user programmable interconnect elements, first ones of said interconnect elements connected between adjoining ones of said segments in a same one of said interconnect conductors, second ones of said interconnect elements connected between intersections of selected ones of said first and second segments, third ones of said interconnect elements connected between inputs and outputs of said digital logic modules and selected ones of said segments, fourth ones of said interconnect elements connected between the multibit digital output of said at least one analog-to-digital converter and the multibit digital input of said at least one digital-to-analog converter and selected ones of said segments.
Claim 2
Dependent Claim
567 words
An user-configurable integrated circuit architecture, including: a plurality of user-configurable digital logic circuit modules, each of said digital logic module having a plurality of inputs and at least one output, at least one of said digital logic circuit modules including means for configuring said digital logic module by a user to perform one of a plurality of functions; a plurality of user-configurable analog circuit modules, each of said analog circuit modules having an input and an output, at least one of said analog circuit modules including programmable means, programmable by a user, for selecting one or more circuit parameters for said at least one of said analog circuit modules; a plurality of analog input buffers, each one of said analog input buffers having an input and an output; a plurality of analog output buffers, each one of said analog output buffers having an input and an output; a first group of input/output pads, on said integrated circuit, each one of said first group of input output pads communicating with the input of one of said input buffers; a second group of input/output pads on said integrated circuit, each one of said second group of input/output pads communicating with the output of one of said output buffers; at least one analog-to-digital converter having an analog input and a multibit digital output; at least one digital-to-analog converter having a multibit digital input and an analog output; a plurality of user configurable analog switches, first ones of said plurality of analog switches connected between ones of said input/output pads in said first group and the inputs of selected ones of said analog circuit modules, second ones of said analog switches connected between ones of said input/output pads in said second group and the outputs of selected ones of said analog circuit modules, second ones of said analog switches, third ones of said analog switches connected between the outputs of ones of said analog circuit modules and the analog input of said at least one analog-to-digital converter, fourth ones of said analog switches connected between the analog output of said at least one analog-to-digital converter and selected ones of said analog circuit modules and said input/output pads of said second group; a plurality of interconnect conductors associated with said plurality of digital logic circuit modules, the multibit digital output of said at least one analog-to-digital converter and the multibit digital input of said at least one digital-to-analog converter, each of said interconnect conductors divided into one or more segments, at least some first ones of said segments running in a first direction and at least some second ones of said segments running in a second direction different from said first direction so as to form intersections between said first ones and second ones of said segments; a plurality of user programmable interconnect elements, first ones of said interconnect elements connected between adjoining ones of said segments in a same one of said interconnect conductors, second ones of said interconnect elements connected between intersections of selected ones of said first and second segments, third ones of said interconnect elements connected between inputs and outputs of said digital logic modules and selected ones of said segments, fourth ones of said interconnect elements connected between the multibit digital output of said at least one analog-to-digital converter and the multibit digital input of said at least one digital-to-analog converter and selected ones of said segments.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.