EP0499178A1
Expired / Lapsed
EP
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System clock switching mechanism for microprocessor
Assignee: NEC Corp
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Filing: 1992-02-10
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Granted: —
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Expires: 2012-02-10
Abstract
Abstract This system clock switching mechanism for a microprocessor has system clock specification data for the tasks in holding means such as a task control block (TDB) (60). If there is no task in READY or RUN status, the clock switching control unit (40) switches the system clock to the low speed clock. When the task is put in RUN status, the system clock specification data for that task in TDB (60) is referred to so that the system clock is switched to the clock as specified.
Inventors
- 👤 Motoki C/O Nec Corporation Ide
- 👤 Toshiharu c/o NEC Corporation Kai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 02:25
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/329; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
96 words
A system clock switching mechanism for a microprocessor comprising a clock generating means (10,11) for supplying a plurality of system clocks at different speeds to the microprocessor (1), a holding means (60) for setting and holding a system clock specification data for each task executed by said microprocessor (1), and a clock switching means (40) for switching the system clock supplied by said clock generating means (10,11); said clock switching means (40) switching the system clock to the one specified for the task according to the system clock specification data held by said holding means (60).
Claim 2
Dependent Claim
65 words
A system clock switching mechanism for a microprocessor of Claim 1 wherein said clock switching means (40) switches the system clock to the lowest speed clock when no task is in READY or RUN status, and when any task is in such a status, to the system clock specified for that task according to the system clock specification data held by said holding means (60).
Claim 3
Dependent Claim
35 words
A system clock switching mechanism for a microprocessor of Claim 1 or 2, wherein the clock generating means (10,11) provides two system clocks: one at a low speed and the other at a high speed.
Claim 4
Independent Claim
173 words
A system clock switching mechanism for a microprocessor comprising a clock generating means (10,11) for supplying a plurality of system clocks at different speeds to the microprocessor, a holding means (60) for setting and holding a system clock specification data for each task executed by said microprocessor (1), a scheduler means (30) for judging whether there is a task in READY or RUN status and refer to the system clock specification data in said holding means (60) for each task, and a clock switching means (40) for switching the system clock supplied from said clock generating means (10,11); said scheduler means (30) causing said clock switching means (40) to switch the system clock to the lowest speed clock when it judges that there is no task in READY or RUN status and instructing said clock switching means (40) to switch the system clock to the clock given by the system clock specification data, and said clock switching means (40) switching the system clock according to the switching instruction from said scheduler means (30).
Claim 5
Dependent Claim
33 words
A system clock switching mechanism for a microprocessor of Claim 4 wherein the clock generating means (10,11) provides two system clocks: one at a low speed and the other at a high speed.
References Cited (Backward Citations)
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