EP0256594A2 — Data processing apparatus with energy saving cloc…

Claim 1

Independent Claim 270 words

A data processing apparatus comprising: - a data processing element, having an operating mode and a stop mode, said element comprising a data input a first data output, a reset signal input, a clock input a stop signal output and first power supply terminal means; - oscillator means for feeding said clock input with clock pulses, said oscillator means having second power supply terminal means; - a data receiving module for receiving external data, said module having a second data output connected to the data input; wherein said dataprocessing element has reset means for under combined control of a series of clock pulses and a reset signal on said reset input attaining an initial state within a predetermined time interval, characterized in that the data processing apparatus further comprises: - switching means, interconnected between said second power supply terminal means and said oscillator means, the switching means having a first control input for detecting an interrupt signal produced by said data receiving module for thereupon driving said switching means to an operating power transmitting state for said second supply terminal means and a second control input fed by said stop signal output for upon detection of a stop signal generated by said data processing element driving said switching means to a stand-by power transmitting state for said second supply terminal means; - a transition signal detector connected betweensaid switching means and said reset signal input for upon detecting any transition from said stand-by power transmitting state to said operating power transmitting state generating a reset pulse, that has a trailing edge occurring only after termination of said predetermined time interval.

Claim 2

Dependent Claim 270 words

A data processing apparatus comprising: - a data processing element, having an operating mode and a stop mode, said element comprising a data input a first data output, a reset signal input, a clock input a stop signal output and first power supply terminal means; - oscillator means for feeding said clock input with clock pulses, said oscillator means having second power supply terminal means; - a data receiving module for receiving external data, said module having a second data output connected to the data input; wherein said dataprocessing element has reset means for under combined control of a series of clock pulses and a reset signal on said reset input attaining an initial state within a predetermined time interval, characterized in that the data processing apparatus further comprises: - switching means, interconnected between said second power supply terminal means and said oscillator means, the switching means having a first control input for detecting an interrupt signal produced by said data receiving module for thereupon driving said switching means to an operating power transmitting state for said second supply terminal means and a second control input fed by said stop signal output for upon detection of a stop signal generated by said data processing element driving said switching means to a stand-by power transmitting state for said second supply terminal means; - a transition signal detector connected betweensaid switching means and said reset signal input for upon detecting any transition from said stand-by power transmitting state to said operating power transmitting state generating a reset pulse, that has a trailing edge occurring only after termination of said predetermined time interval.

Claim 3

Dependent Claim 107 words

A data processing apparatus as claimed in Claim 1, characterized in that said switching means comprise a reset-set-latch having its reset input fed by an interrupt-signal-detector that is connected to said first control input for detecting the interrupt signal produced by said data receiving module, its set input connected to a stoij-signal detector that is connected to said second control input and that is fed by said stop signal output for detecting the stop signal, and having an output terminal connected to a control electrode of a transistor, that has its conduction path connected between an input of said transition-signal detector and said second power supply means.

Claim 4

Dependent Claim 273 words

A data processing apparatus as claimed in Claim 1 or 2, wherein said data processing element has, within a frequency interval of interest, in its operating mode a current I - versus - freqeuncy f - characteristic approximated by I = x f + β, an additional mode of reduced activity (idle mode) in which mode said data processing element has within the frequency interval of interest a current I - versus - frequency f - characteristic approximated by I = Σf + λ, all of α, β, Σ and λ being larger than zero, in its stop mode a current I = ϑ«β passing through it, a settling time t o , and is used for the execution of an average number of N instructions between two of said successive interrupts, the average interrupt rate being one interrupt per period T, T > 2t o , while the average number of clock cycles per instruction equals a number C, depending on the type of said data processing element, characterized in that, when is smaller than X + (X²-Y) ½ , the frequency f of the clock pulses fed by said oscillator means lies in the frequency interval X - (X² - Y) ½ }≦f ≦ X + (X² - Y) ½ wherein X ≈ (((β - λ) (ΣT+2t o α)NC) ½ )/2t o α+(λT-NC Σ)/4t o for keeping the average energy consumption of said data processing element when switched between said operating mode and said stop mode below the minimum average energy consumption of said data processing element that can be attained by switching between said operating mode and said idle mode.

Claim 5

Dependent Claim 114 words

A data processing apparatus as claimed in Claim 1 or 2, characterized in that when the expression: is valid, the frequency f of the clock pulses fed by said oscillator means lies in the frequency interval: wherein P ≈ ((NCβ)/(2t o α)) ½ + 0.1 . {((NCβ)/(2t o α)) ½ + β/2α + NC/4t o α + ϑT/4t o α} and that when the expression: is valid, the frequency f of the clock pulses fed by said oscillator means lies in the frequency interval: wherein R≈NC/2T + β T/4αt o + 0.1 (NC/4t o + βT/4αt o ) for attaining an average energy consumption of at most 1.1 times the minimum average energy consumption.

Claim 6

Dependent Claim 184 words

A data processing apparatus as claimed in any of Claims 1, 2, 3 or 4 comprising at least a first and a second data receiving module, each having a respective second data output for forwarding data to said data processing element and a respective interrupt signal output for foresending the interrupt signal characterized in that the data processing apparatus furthermore comprises: - a selection means fed in parallel by said second data output and fed in parallel by said interrupt signal outputs, said selection means having: - first gating means for gating a first received interrupt signal to said first control input; - second gating means for gating data sssociated to said first received interrupt signal to said data processing element; - disabling means for upon reception of said first received interrupt signal disabling said first and second gating means for gating any interrupt signal or data from another data receiving module than the one generating said first received interrupt signal; - enabling means connected to said second control input for upon reception of said stop signal reenabling said first and second gating means.

Claim 7

Dependent Claim 208 words

A data processing apparatus as claimed in Claim 2 and 5, having a number of j ≧ 2 data receiving modules, each having a respective second data output and a respective interrupt signal output characterized in that said selection means comprises: - a number of j reset-set-latches, each having its set terminal connected to said stop-signal detector; - a number of j AND-gating means, each having (j-1) gate inputs and connecting a respective interrupt signal output to an associated reset terminal; - a number of j interface gating means, each connecting a respective second data output to the data input and having a blocking state, a passing state and a state control input connected to a first output terminal of an associated reset-set-latch, for upon reception of a blocking-signal being driven go the blocking state and upon reception of a pass-signal being driven to the passing state; - a j-input OR-gating means fed by said j reset terminals and feeding the interrupt-signal detector; wherein AND-gating means of rank number k, 1 ≦ k ≦ j, connecting data receiving module number k to reset-set-latch number k, has its (j-1) gate input connected to respective second output terminals of reset-set-latches with numbers m ≠ k, 1 ≦ m ≦ j.

Claim 8

Dependent Claim 74 words

A data processing apparatus as claimed in Claim 5 or 6, characterized in that said oscillator means comprise a plurality of oscillator circuits, each for generating clock pulses of an associated frequency, and a selection input connected to said selection means for upon reception of a selection signal thereupon selecting one oscillator circuit to be connected to said clock output, between said selection means receiving an interrupt signal and the next following stop signal.

Claim 9

Dependent Claim 47 words

A data processing apparatus as claimed in any of the preceding Claims, characterized in that while said data processing element is in said stop mode a resistor is connected between said second power supply terminal means and said oscillator means, as a pass-by for a stand-by current.

Claim 10

Dependent Claim 42 words

A data processing apparatus as claimed in any of the preceding Claims, characterized in that the data processing apparatus further comprises first amplifier means having third power supply terminal means connected to said second supply terminal means, for amplifying said clock pulses.

Claim 11

Dependent Claim 43 words

A data processing apparatus as claimed in any of the preceding Claims, characterized in that the data processing apparatus further comprises second amplifier means having fourth power supply terminal means connected to said second power supply terminal means, for amplifying said stop signal.

Claim 12

Dependent Claim 29 words

A data processing apparatus as claimed in any one of the preceding Claims, characterized in that at least one data controlled module is connected to said first data output.

Claim 13

Dependent Claim 14 words

A data processing apparatus substantially as described herein with reference to the accompanying drawings.

Claim 14

Dependent Claim 14 words

A data processing apparatus substantially as described herein with reference to the accompanying drawings.

Claim 15

Dependent Claim 27 words

A data processing apparatus substantially as described herein with reference to Figures 1 to 4 or to Figure 6 or to Figure 7 of the accompanying drawings.

Claim 16

Dependent Claim 27 words

A data processing apparatus substantially as described herein with reference to Figures 1 to 4 or to Figure 6 or to Figure 7 of the accompanying drawings.

Data processing apparatus with energy saving clocking device

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag