Patent EP0496928A2 successfully refreshed from Google Patents.
EP0496928A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Compounding preprocessor for cache
Assignee: International Business Machines Corp
•
Filing: 1991-04-03
•
Granted: —
•
Expires: 2011-04-03
Abstract
Abstract A digital computer system is described capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
Inventors
- 👤 Stamatis Vassiliadis
- 👤 Bartholomew Blaner
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 12:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/30145; G06F9/30149; G06F9/30152; G06F9/3017; G06F9/3802; G06F9/3808; G06F9/3812; G06F9/3836; G06F9/3842; G06F9/3853; G06F9/3885
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
101 words
In a digital computer system capable of processing two or more instructions in parallel, the combination comprising: a larger-capacity, lower-speed storage mechanism for storing instructions to be processed; a smaller-capacity, higher-speed storage mechanism for storing instructions with associated tag information; and an instruction compounding mechanism coupled between the lower-speed storage mechanism and the higher-speed storage mechanism for receiving instructions from the lower-speed storage mechanism, for analyzing these instructions and producing tag information which indicates which instructions may be processed in parallel with one another and for supplying these instructions and associated tag information to the higher-speed storage mechanism for storage therein.
Claim 2
Dependent Claim
15 words
The combination of claim 1 wherein the higher-speed storage mechanism is a cache storage mechanism.
Claim 3
Dependent Claim
34 words
The combination of claim 1 or 2 wherein the tag information is comprised of a plurality of tags, a different one of which is associated with each instruction analyzed by the instruction compounding mechanism.
Claim 4
Dependent Claim
52 words
The combination of one of claims 1 to 3 wherein the computer system includes a plurality of functional instruction processing units which operate in parallel with one another and the tag information is used in issuing two or more instructions from the higher-speed storage mechanism to different ones of the functional units.
Claim 5
Dependent Claim
94 words
The combination of claim 3 or 4 wherein the instruction compounding mechanism includes: a plural-instruction instruction register for receiving a plurality of successive instructions from the lower-speed storage mechanism; a plurality of rule-based instruction analyzer mechanisms, each of which analyzes a different pair of side-by-side instructions in the instruction register and produces a compoundability signal which indicates whether or not the two instructions in its pair may be processed in parallel; and a tag generating mechanism responsive to the compoundability signals for generating the individual tags for the different instructions in the instruction register.
Claim 6
Dependent Claim
59 words
The combination of claim 5 wherein: the computer system has a particular instruction processing configuration; and each instruction analyzer mechanism includes logic circuitry for implementing rules which define which types of instructions are compatible for parallel execution in the particular instruction processing configuration used for the computer system, such logic circuitry producing the compoundability signal for that analyzer mechanism.
Claim 7
Dependent Claim
133 words
In a digital computer system capable of processing two or more instructions in parallel, the combination comprising: a first storage mechanism for storing instructions to be processed; an instruction compounding mechanism for receiving instructions from the first storage mechanism and associating with these instructions compounding information which indicates which of these instructions may be processed in parallel with one another; a further storage mechanism coupled to the instruction compounding mechanism for receiving and storing the instructions and their associated compounding information; a plurality of functional instruction processing units which operate in parallel with one another; and an instruction issue mechanism coupled to the further storage mechanism for supplying adjacent instructions stored therein to different ones of the functional instruction processing units when their compounding information indicates that they may be processed in parallel.
Claim 8
Dependent Claim
17 words
The combination of claim 7 wherein the further storage mechanism is a small-capacity, high-speed cache storage mechanism.
Claim 9
Dependent Claim
92 words
In a digital computer system including means for executing two or more instructions and a main memory and cache for storing instructions, a method for processing instructions for parallel execution, the method comprising the steps of: storing a plurality of instructions in the main memory; obtaining a sequence of instructions from the main memory for execution; in response to the sequence of instructions, generating compounding information signifying parallel execution of at least two instructions in the sequence of instructions; and storing the sequence of instructions and the compounding information in the cache.
Claim 10
Dependent Claim
36 words
The method of Claim 9, wherein the plurality of instructions are in object code format and the step of generating includes generating the compounding information without altering the object code format of the sequence of instructions.
Claim 11
Dependent Claim
24 words
The method of Claim 9 or 10, wherein the step of storing in the cache includes storing the compounding information only in the cache.
Claim 12
Independent Claim
84 words
The method of one of claims 9 to 11, wherein the digital computer system includes means for providing a cache miss signal when an instruction to be executed is not in the cache, the method further including the step of repeatedly, until a cache miss occurs, (1) obtaining from the cache at least two instructions of the sequence of instructions together with compounding information for the two instructions and (2) in response to the compounding information, executing the at least two instructions in parallel.
Claim 13
Dependent Claim
37 words
The method of Claim 12, further including, when a cache miss occurs, executing the steps of obtaining a sequence of instructions, generating compounding information, and storing the sequence of instructions and the compounding information in the cache.
Claim 14
Independent Claim
49 words
The method of one of claims 9 to 13, wherein the digital computer system includes means for providing a cache miss signal when an instruction to be executed is not in the cache, the step of obtaining including fetching the instruction sequence in response to the cache miss signal.
Claim 15
Dependent Claim
59 words
The method of Claim 14, further including the steps of: prefetching a sequence of instructions from the main memory; in response to the prefetched sequence of instructions, generating compounding information signifying parallel execution of at least two adjacent instructions in the prefetched sequence of instructions; and storing the second sequence of instructions and the compounding information in the cache.
Claim 16
Independent Claim
27 words
The method of one of claims 9 to 15, further including the step of: concurrently with the generating step, executing an instruction of the sequence of instructions.
Claim 17
Independent Claim
47 words
The method of one of claims 9 to 16 further including the steps of: executing an instruction of the sequence of instructions; as a result of executing the instruction, altering the sequence of instructions; obtaining the altered sequence of instructions; and repeating the generating and storing steps.
Claim 18
Independent Claim
158 words
An apparatus for processing a sequence of compiled instructions for parallel execution, comprising: buffer means for receiving a sequence of compiled instructions; categorization means responsive to the sequence of compiled instructions for: determining whether two or more instructions belong to predetermined categories of instructions; and providing first signals conditioned to indicate to which predetermined categories the two or more instructions belong; interlock means responsive to the sequence of compiled instructions for providing second signals conditioned to indicate whether interlocks exist between the two or more instructions; compounding signal means connected to the categorization and interlock means and responsive to the first and second signals for providing a compounding signal conditioned to indicate whether the at least two instructions belong to instruction categories compatible for execution in parallel and are interlock-free; and storage means connected to the compounding signal means for receiving a plurality of compounding signals for the sequence of instructions during operation of the compounding signal means.
Claim 19
Dependent Claim
59 words
The apparatus of Claim 18, wherein the compounding signal means includes rule means responsive to the first and second signals for: testing the conditions of the first and second signals according to a set of rules, the set of rules establishing which categories of instructions can be executed in parallel and establishing exceptions to those rules resulting from interlocks.
Claim 20
Dependent Claim
19 words
The apparatus of Claim 18 or 19, wherein the sequence of instructions includes a portion of a cache line.
Claim 21
Independent Claim
18 words
The apparatus of one of claims 18 to 20, wherein the categorization means includes means for decoding instructions.
Claim 22
Independent Claim
35 words
The apparatus of one of claims 18 to 21, wherein the compounding signal means includes a programmable device for being selectively programmed to test the first and second signals according to the set of rules.
Claim 23
Independent Claim
28 words
The apparatus of one of claims 18 to 22 further including a high-speed instruction memory means for storing the sequence of compiled instructions and compounding signals for execution.
Claim 24
Dependent Claim
88 words
In a computer system including a plurality of execution units which execute instructions singly and in parallel, a method of processing instructions for parallel execution, including the steps of: generating a sequence of instructions for execution; prior to execution of the sequence of instructions, generating information signals indicating that at least two instructions of the sequence can be executed in parallel; storing the sequence of instructions and the information signals in a storage device to provide fast access for execution; and executing instructions of the sequence of instructions.
Claim 25
Dependent Claim
26 words
The method of Claim 24, further including: during and after the executing step, retaining the sequence of instructions and the information signals in the storage device.
Claim 26
Dependent Claim
160 words
In a computer system with means for executing instructions singly and in parallel and a memory means for receiving a sequence of instructions for imminent execution, a combination for processing sequences of instructions for parallel execution according to a set of rules which establish instruction conditions for parallel execution of instructions, the combination comprising: a means for receiving a sequence of instructions, the sequence of instructions forming a part of a computer program; rule base means connected to the means for receiving for: comparing groups of instructions in the sequence of instructions to determine whether the instructions of the groups of instructions satisfy rules of the set of rules; and generating compounding signals conditioned to indicate instructions of a group of instructions which can be executed in parallel; and storage means connected to the rule base means and to the memory means for accumulating a plurality of compounding signals for storage in the memory means with the sequence of instructions.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.