Constant-voltage generating circuit

Abstract

Abstract In a constant-voltage generating circuit wherein a first series circuit of PMOS transistors (QP1,QP2), a second series circuit of a PMOS transistor (QP3) and an NMOS transistor (QN1) and a third series circuit of PMOS transistors (QP4,QP5) are connected between a power source line (VCC) and a ground line (GND), a capacitive element (QNC) is connected between a common junction node (N1) of the PMOS transistors (QP1,QP2) of the first series circuit and the ground line (GND). In addition to this capacitive element, another capacitive element (QPC) may be connected between the node and the power source line. Since the node (N1) is connected to gates of one (QP1) of the PMOS transistors of the first series circuit and the PMOS transistor (QP3) of the second series circuit, the capacitance at this node with respect to the power source line is large. Thus, when the power supply voltage fluctuates abruptly, the voltage at the first node also changes and thus the output voltage (VREF) also changes. This phenomenon can be suppressed by the action of the capacitive element connected between the common junction node of the first series circuit and the ground line. <IMAGE>

Inventors

• 👤 Shingo c/o Nec Ic Microcomputer Sys. Ltd. Aizaki

Bibliographic Details