Parallel pipelined instruction processing system for very long instruction word

Claim 1

A parallel pipelined instruction processing system for processing "n" instructions in parallel (where "n" is a natural number not less than 2), the system comprising: first memory means storing a number of instruction blocks each including "n" instructions arranged in parallel; instruction block fetch means for fetching an instruction block from said first memory means; "n" instruction processing means each processing a corresponding instruction of the "n" instructions included in the instruction block read from the instruction block fetch means; second memory means storing operandi used by said instruction processing means, said second memory means being able to be read and written independently of said instruction processing means, each of said instruction processing means including an input operand fetch means for fetching from said second memory means an input operand necessary for execution of said corresponding instruction, instruction execution means for executing said corresponding instruction by using the input operand supplied from said input operand fetch means, and result operand write means for writing back to said second memory meal's a result operand obtained by execution of said corresponding instruction by said instruction execution means, the system also comprising: a short path means for directly supplying a result operand obtained by execution of an instruction by one instruction execution means, to the same instruction execution means which executed an instruction which needs said result operand as an input operand and which is included in an instruction block later than the instruction block including said instruction by one machine cycle; so that the instruction block fetching and the input operand reading are performed concurrently, and then, the instruction processing and the short path processing are performed concurrently, and thereafter, the result operand writing is performed, whereby an instruction other than the branch instruction is executed by the pipelined processing, the system further comprising: a next address generation means for generating an address for an instruction block to be executed next to the instruction block being executed; a branch address generation means for generating an address for a branch destination instruction block; a second short path means for directly supplying said next address generated by said next address generation means, to a predetermined instruction execution means which executes an instruction which needs said next address as an input operand and which is included in an instruction block later than the instruction block being executed, by one machine cycle; so that the next instruction block reading and the next address generation are performed in parallel, and then, the input operand reading and the branch address generation are performed in parallel, and thereafter, the short path processing is performed, and then, the result operand writing is performed, whereby the branch instruction is executed by the pipelined processing.