Patent EP0495452A2 successfully refreshed from Google Patents.
EP0495452A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Field effect transistor
Assignee: Sumitomo Electric Industries Ltd
•
Filing: 1992-01-14
•
Granted: —
•
Expires: 2012-01-14
Abstract
Abstract The invention provides a FET by forming a channel layer (33) including "n" type impurity at high concentration, said channel layer (33) being sandwiched by a first semiconductor layer (32) and a second semiconductor layer (34) lightly doped with impurity. Therefore, even when electrons in the channel layer (33) obtain high energy, the electrons in this arrangement rush out essentially to the second semiconductor layer (34) excelling in electron carrying characteristic, thus travelling speed of the electrons in the channel layer (33) is not lowered. Furthermore, as the channel layer (33) is thinly formed and allowed to include impurity at high concentration, the current drive capability can be improved.
Inventors
- 👤 Shigeru C/O Yokohama Works Of Nakajima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 09:20
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/877
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
128 words
A field effect transistor comprising: a first semiconductor layer (32; 43), a channel layer (33; 44) having a crystalline structure substantially lattice-matching the first semiconductor layer (32; 43), the channel layer (33; 34) being thinly formed containing an "n" type impurity at a high concentration, a second semiconductor layer (34; 45) having a crystalline structure substantially lattice-matching the channel layer (33; 44), the second semiconductor layer (34; 54) being lightly doped with impurity made of materials with a higher electron carrying characteristic than that of the channel layer (33; 44), and a third semiconductor layer (35; 46) in heterojunction with the second semiconductor layer (34; 45), the third semiconductor layer (35; 46) being lightly doped with impurity and being in Schottky contact with a gate electrode (40; 51).
Claim 2
Dependent Claim
24 words
A field effect transistor as claimed in claim 1, wherein the first semiconductor layer (32; 43) is formed on a semiconductor substrate (31; 41).
Claim 3
Dependent Claim
44 words
A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises a semiconductor substrate (41) and a buffer layer (42) formed on the semiconductor substrate (41), and the first semiconductor layer (43) is formed on the buffer layer (42).
Claim 4
Dependent Claim
26 words
A field effect transistor as claimed in any of the claims 1 to 3, wherein the first semiconductor layer (32; 43) is lightly doped with impurity.
Claim 5
Dependent Claim
49 words
A field effect transistor as claimed in any of the claims 1 to 4, wherein the field effect transistor further comprises a contact layer (36; 47) formed on the third semiconductor layer (35; 46) and an ohmic electrode (37, 38; 48, 49) formed on the contact layer (36; 47).
Claim 6
Dependent Claim
35 words
A field effect transistor as claimed in any of the claims 1 to 5, wherein the gate electrode (40; 51) is formed on a recess (39; 50) formed on the third semiconductor layer (35; 46).
Claim 7
Dependent Claim
52 words
A field effect transistor as claimed in any of the claims 1 to 6, wherein the channel layer (33) is made of InP and the third semiconductor layer (35) is made of Al x In 1-x As with a composition ratio X of Al of 0.4 or more and 0.6 or less.
Claim 8
Dependent Claim
202 words
A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises a semi-insulative InP semiconductor substrate (31), the first semiconductor layer (32) is formed on said semi-insulative InP semiconductor substrate (31), the first semiconductor layer being made of undoped InP, the channel layer (33) is formed on the first semiconductor layer, the channel layer (33) being made of n⁺ type InP doped with Si at a high concentration, the second semiconductor layer (34) is formed on the channel layer (33), the second semiconductor layer (34) being made of undoped InP, the third semiconductor layer (35) is formed on the second semiconductor layer (34), the third semiconductor layer (35) being made of undoped Al x In 1-X As with a composition ratio X of Al of 0.4 or more and 0.6 or less, and the field effect transistor further comprises: a contact layer (36) made of n⁺ type InGaAs formed on the third semiconductor layer (35), a gate electrode (40) in Schottky contact with said third semiconductor layer (35) exposed on a recess (39) formed on the contact layer (36) and said third semiconductor layer (35), and an ohmic electrode (37, 38) formed on said contact layer (36).
Claim 9
Dependent Claim
42 words
A field effect transistor as claimed in claim 8, wherein a first semiconductor layer and a second semiconductor layer made of undoped InGaAs are provided instead of the first semiconductor layer (32) and the second semiconductor layer (34) made of undoped InP.
Claim 10
Dependent Claim
30 words
A field effect transistor as claimed in claim 8 or 9, wherein an undoped InGaAs layer is provided between the second semiconductor layer (34) and the third semiconductor layer (35).
Claim 11
Dependent Claim
51 words
A field effect transistor as claimed in any of the claims 1 to 6, wherein the channel layer (33) is made of GaAs and the third semiconductor layer (35) is made of Al x Ga 1-X As with a composition ratio X of Al of above zero and 0.3 or less.
Claim 12
Dependent Claim
212 words
A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises a semi-insulative GaAs semiconductor substrate (31), the first semiconductor layer (32) is formed on the semi-insulative GaAs semiconductor substrate (31), the first semiconductor layer (32) being made of substantially undoped p⁻ type GaAs, the channel layer (33) is formed on the first semiconductor layer (32), the channel layer (33) being made of n⁺ type GaAs doped with Si at a higher concentration, the second semiconductor layer (34) is formed on the channel layer (33), the second semiconductor layer (34) being made of substantially undoped n⁻ type GaAs, the third semiconductor layer (35) is formed on the second semiconductor layer (34), the third semiconductor layer (35) being made of substantially undoped n⁻ type Al X Ga 1-X As with a composition ratio X of Al of above zero and 0.3 or less, and the field effect transistor further comprises: a contact layer (36) made of n⁺ type GaAs formed on the third semiconductor layer (35), a gate electrode (40) in Schottky contact with said third semiconductor layer (35) exposed on a recess (39) formed on the contact layer (36) and said third semiconductor layer (35), and an ohmic electrode (37, 38) formed on said contact layer (36).
Claim 13
Dependent Claim
66 words
A field effect transistor as claimed in claim 12, wherein a first semiconductor layer made of substantially undoped p⁻ type InGaAs is provided instead of the first semiconductor layer (32) made of a substantially undoped p⁻ type GaAs, and a second semiconductor layer made of substantially undoped n⁻ type InGaAs is provided instead of the second semiconductor layer (34) made of substantially undoped n⁻ type GaAs.
Claim 14
Dependent Claim
71 words
A field effect transistor as claimed in any of the claims 1 to 6, wherein the channel layer (44) is made of In Y Ga 1-Y As with a composition ratio Y of In of 0.45 or more and 0.65 or less, and the third semiconductor layer (46) is made of Al x In 1-Y As with a composition ratio X of Al of 0.4 or more and 0.6 or less.
Claim 15
Dependent Claim
249 words
A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises: a semi-insulative InP semiconductor substrate (41) and a buffer layer (42) made of undoped AlInAs for lattice-matching the semi-insulative InP semiconductor substrate (41), the first semiconductor layer (43) is formed on the buffer layer (42), the first semiconductor layer (43) being made of undoped In Y Ga 1-Y As with a composition ratio Y of In of 0.45 or more and 0.65 or less, the channel layer (44) is formed on the first semiconductor layer (43), the channel layer (44) being made of n⁺ type of said In Y Ga 1-Y As doped with Si at a higher concentration, the second semiconductor layer (45) is formed on the channel layer (44), the second semiconductor layer (45) being made of said undoped In Y Ga 1-Y As, the third semiconductor layer (46) is formed on the second semiconductor layer (45), the third semiconductor layer (46) being made of undoped Al X In 1-X As with a composition ratio X of Al of 0.4 or more and 0.6 or less, and the field effect transistor further comprises: a contact layer (47) made of n⁺ type InGaAs formed on the third semiconductor layer (46), a gate electrode (51) in Schottky contact with said third semiconductor layer (46) exposed on a recess (50) formed on the contact layer (47) and said third semiconductor layer (46), and an ohmic electrode (48, 49) formed on said contact layer (47).
Claim 16
Dependent Claim
44 words
A field effect transistor as claimed in claim 15, wherein a first semiconductor layer and a second semiconductor layer made of undoped InP are provided instead of the first and second semiconductor layers (43, 45) made of the undoped In Y Ga 1-Y As.
Claim 17
Dependent Claim
71 words
A field effect transistor as claimed in any of the claims 1 to 6, wherein the channel layer (44) is made of In Y Ga 1-Y As with a composition ratio Y of In of zero or more and 0.35 or less, and the third semiconductor layer (46) is made of Al X Ga 1-X As with a composition ratio X of Al of zero or more and 0.3 or less.
Claim 18
Dependent Claim
248 words
A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises: a semi-insulative GaAs semiconductor substrate (41), and a buffer layer (42) made of undoped GaAs for lattice-matching the semi-insulative GaAs semiconductor substrate (41), the first semiconductor layer (43) is formed on the buffer layer (42), the first semiconductor layer (43) being made of undoped In Y Ga 1-Y As with a composition ratio Y of In of zero or more and 0.35 or less, the channel layer (44) is formed on the first semiconductor layer (43), the channel layer (44) being made of said n⁺ type In Y Ga 1-Y As doped with Si at a high concentration, the second semiconductor layer (45) is formed on the channel layer (44), the second semiconductor layer (45) being made of said undoped In Y Ga 1-Y As, the third semiconductor layer (46) is formed on the second semiconductor layer (45), the third semiconductor layer (46) being made of undoped Al X Ga 1-X As with a composition ratio X of Al of zero or more and 0.3 or less, and the field effect transistor further comprises: a contact layer (47) made of n⁺ type InGaAs formed on the third semiconductor layer (46); a gate electrode (51) in Schottky contact with said third semiconductor layer (46) exposed on a recess (50) formed on the contact layer (47) and said third semiconductor layer (46), and an ohmic electrode (48, 49) formed on said contact layer (47).
Claim 19
Dependent Claim
43 words
A field effect transistor as claimed in claim 18, wherein a first semiconductor layer and a second semiconductor layer made of undoped GaAs are provided instead of the first and second semiconductor layers (43, 45) made of undoped In Y Ga 1-Y As.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.