Patent EP0381071A2 successfully refreshed from Google Patents.
Patent EP0495329A2 successfully refreshed from Google Patents.
EP0495329A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
High performance/high density bicmos process
Assignee: International Business Machines Corp
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Filing: 1991-12-17
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Granted: —
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Expires: 2011-12-17
Abstract
Abstract An integrated circuit using high-performance bipolar and CMOS transistor elements on a single chip is fabricated by a simplified process requiring minimal, if any, changes in the process used for forming either type of device in accordance with a variety of possible device designs. The method according to the invention makes maximal use of self-aligned and self-masking processes to reduce the number of processing steps. The number of processing steps is further reduced by performing some steps concurrently on different device types. Further, the masking steps which are employed are reasonably misregistration tolerant, resulting in high manufacturing yield for the process. Consequently, the process according to the invention substantially eliminates the existence of trade-offs between element performance, integration density and process complexity and cost when plural technologies are integrated on the same chip.
Inventors
- 👤 Michael Monkowski
- 👤 Seiki Ogura
- 👤 Nivo Rovedo
- 👤 Joseph Francis Shepard
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 21:39
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10P32/14; H10P32/1408; H10P32/1414; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
87 words
A process for manufacturing an integrated circuit device including circuit elements formed according to both CMOS and bipolar technologies including the steps of simultaneously forming portions of circuit elements according to both said CMOS and said bipolar technologies, masking said circuit elements according to said bipolar technology and partially completing said circuit elements according to said CMOS technology, masking said circuit elements according to said CMOS technology and completing said circuit elements according to said bipolar technology, and completing said circuit elements according to said CMOS technology.
Claim 2
Dependent Claim
104 words
A process for manufacturing an integrated circuit device including circuit elements formed according to both CMOS and bipolar technologies including the steps of simultaneously forming portions of circuit elements according to both said CMOS and said bipolar technologies, masking said circuit elements according to said bipolar technology and partially completing said circuit elements according to said CMOS technology, masking said circuit elements according to said CMOS technology and partially completing said circuit elements according to said bipolar technology, simultaneous forming further portions of circuit elements according to both said CMOS and said bipolar technologies, and completing said circuit elements according to said CMOS technology.
Claim 3
Dependent Claim
44 words
A process as recited in claim 2, wherein said step of masking said circuit elements according to said bipolar technology and partially completing said circuit elements according to said CMOS technology includes formation of a portion of a circuit element using a self-aligned process.
Claim 4
Dependent Claim
44 words
A process as recited in claim 2, wherein said step of masking said circuit elements according to said CMOS technology and partially completing said circuit elements according to said bipolar technology includes formation of a portion of a circuit element using a self-aligned process.
Claim 5
Dependent Claim
40 words
A process as recited in claim 2, wherein said step of simultaneously forming further portions of circuit elements according to both said CMOS and said bipolar technologies includes formation of a portion of a circuit element using a self-aligned process.
Claim 6
Dependent Claim
63 words
A process as recited in claim 1, including the further steps of forming source and drain regions of said circuit element formed accorcing to said CMOS technology by implanting an impurity of a first conductivity type, diffusing said impurity of said first conductivity type, implanting an impurity of a second conductivity type, and diffusing said impurities of said first and second conductivity types.
Claim 7
Dependent Claim
73 words
A process as recited in claim 1, further including the steps of masking all portions of a substrate including isolation trench structures other than areas between said isolation trench structures and an area of a substrate in which one of said circuit element formed accorcing to said CMOS technology is to be formed, and forming channel stop regions though said mask by implantation of impurities of a conductivity opposite that of said substrate.
Claim 8
Dependent Claim
74 words
A process as recited in claim 1, further including the step of defining the extent of at least one of an emitter connection and a base connection from a continuous layer also forming at least one of an emitter and a base of said circuit element formed according to said bipolar technology including the further steps of applying a mask in the vicinity of said transistor and etching unmasked areas of said continuous layer.
Claim 9
Dependent Claim
35 words
A process as recited in claim 1, including the further step of implanting an impurity in a polysilicon layer forming a base region of a plurality of said devices formed according to said bipolar technology.
Claim 10
Dependent Claim
116 words
A process as recited in claim 1, further including the step of forming a base region of a circuit element formed according to said bipolar technology, said step of forming a base region including the steps of forming a base connection region as a layer of highly doped semiconductor material contacting a substrate at a predetermined location, forming an extrinsic base region by diffusing said impurity from said layer of highly doped semiconductor material into said predetermined area of said substrate, implanting an impurity into an area of said substrate adjacent said predetermined area to form an intrinsic base, and annealing said substrate to further diffuse said impurities until said intrinsic base contacts said extrinsic base.
Claim 11
Dependent Claim
59 words
A process as recited in claim 1, wherein said integrated circuit has some connections to said circuit elements thereon formed as exposed silicon surfaces, including the steps of masking selected areas of said integrated circuit, forming connection openings to expose other portions of silicon surfaces, removing said mask, and simultaneously depositing a metal silicide on all exposed silicon surfaces.
References Cited (Backward Citations)
No citation records indexed.
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