Patent EP0495162A2 successfully refreshed from Google Patents.
EP0495162A2
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Storage management
Assignee: International Business Machines Corp
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Filing: 1991-10-28
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Granted: —
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Expires: 2011-10-28
Abstract
Abstract In a computer system having a system memory (12), m architected logical register and an array (30) of n physical registers, where n is greater than m, a method of managing storage operands including the steps of: detecting the decoding of an instruction having at least one field specifying a storage operand; identifying an available one of the physical registers; fetching the storage operand from the system memory; loading the storage operand into the available one of the physical registers; and executing the instruction, using the storage operand stored in the one of the physical registers.
Inventors
- 👤 Viktors Berstis
- 👤 John Stephen Liptay
- 👤 Raymond James Pedersen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 18:43
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/355; G06F9/38; G06F9/3824; G06F9/3826; G06F9/3836; G06F9/3838; G06F9/384
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
97 words
Computer system having a system memory, m architected logical registers and an array of n physical registers, where n is greater than m, a method of managing storage operands characterized by the steps of: detecting the decoding of an instruction having at least one field specifying a storage operand; identifying an available one of the physical registers (30); fetching the storage operand from the system memory (12); loading the storage operand into the available one of the physical registers (30); and executing the instruction, using the storage operand stored in the one of the physical registers (30).
Claim 2
Dependent Claim
174 words
Computer system, characterized by a system memory (12), an array of n physical registers (30) in a system architecture comprising m logical registers, n being greater than m; first means for detecting the decoding of an instruction having at least one field specifying a storage operand; second means, coupled to the array of n physical registers, for identifying an available one of the physical registers; third means, coupled to the system memory, for fetching the storage operand from the system memory; fourth means, coupled to the first, second and third means, for loading the storage operand into the available one of the physical registers; fifth means, coupled to the fourth means, for maintaining a correlation between the at least one field specifying the storage operand and the available one of the physical registers; and sixth means, coupled to the array of n physical registers and the fifth means, for executing the instruction using the available one of the physical registers as a source for the storage operand specified by the at least one field.
Claim 3
Dependent Claim
62 words
Computer system according to claim 2, characterized by the steps of: detecting the decoding of a register load instruction having at least one field specifying a storage operand; identifying an available one of the physical registers; fetching the storage operand from the system memory; loading the storage operand into the available one of the physical registers; and bypassing execution of the instruction.
Claim 4
Dependent Claim
149 words
Computer system according to one of claims 1-3, characterized by first means for detecting the decoding of an instruction having at least one field specifying a storage operand, said first means further including indicating means for indicating a type of instruction which has been decoded; second means, coupled to the array of n physical registers, for identifying an available one of the physical registers; third means, coupled to the system memory and the first means, for fetching the storage operand from the system memory; fourth means, coupled to the first, second and third means, for loading the storage operand into the available one of the physical registers; and an execution unit, coupled to the array of n physical registers, and to the first means; said third means further comprising, bypass means for bypassing said execution unit when the indicating means indicates that a register load instruction has been decoded.
References Cited (Backward Citations)
No citation records indexed.
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