Quadrature modulation circuit

Claim 2

A quadrature modulation circuit including at least one low pass filter (20) using ROM for limiting the frequency band-width of the in-phase channel (I) and the quadrature channel (Q), at least one D/A converter (3i, 3q) for converting the digital signal received from the low pass filter (20) to an analog signal, at least one filter (4i, 4q) for suppressing the aliases output from the D/A converter (3i, 3q), a quadrature modulator (5) for modulating a carrier signal with the output from the filter (4i, 4q): wherein the low pass filter (20) uses one symbol data in a set of symbol data as a sign data, and inverts the sign of the remaining symbol data and an output data from a ROM by using the one symbol data.

Claim 3

A quadrature modulation circuit including at least one low pass filter (20) using ROM for limiting the frequency band-width of the in-phase channel (I) and the quadrature channel (Q), at least one D/A converter (3i, 3q) for converting the digital signal received from the low pass filter (20) to an analog signal, at least one filter (4i, 4q) for suppressing the aliases output from the D/A converter (3i, 3q), a quadrature modulator (5) for modulating a carrier signal with the output from the filter (4i, 4q): wherein the low pass filter (20) divides the data into a first half portion and a second half portion, and reads out the contents of the ROM (201) for the forward direction of the time axis at the first half portion, and for the backward direction of the time axis at the second half portion.

Claim 4

The circuit of claim 1, wherein the D/A converter (3i, 3q) converts the digital signal received from the low pass filter (20) to an analog signal by a time division process.

Claim 5

The circuit of claim 1, wherein the low pass filter (20) also uses one symbol data in a set of symbol data as a sign data, and inverts the sign of the remaining symbol data and an output data from a ROM (201) by using the one symbol data.

Claim 6

The circuit of claim 5, wherein the D/A converter (3i, 3q) converts the digital signal received from the low pass filter (20) to an analog signal by a time division process.

Claim 7

The circuit of claim 5, wherein the low pass filter (20) further divides the data into the first half portion and the second half portion, and reads out the contents of the ROM (201) for the forward direction of the time axis at the first half portion, and for the backward direction of the time axis at the second half portion.

Claim 8

The circuit of claim 7, wherein the D/A converter (3i, 3q) converts the digital signal received from the low pass filter (20) to an analog signal by a time division process.

Claim 9

The circuit of claim 1, wherein the low pass filter (20) further divides the data into a first half portion and a second half portion, and reads out the contents of the ROM (201) for the forward direction of the time axis at the first half portion, and for the backward direction of the time axis at the second half portion.

Claim 10

The circuit of claim 9, wherein the D/A converter (3i, 3q) converts the digital signal received from the low pass filter (20) to an analog signal by a time division process.

Claim 11

The circuit of claim 2, wherein the low pass filter (20) further divides the data into a first half portion and a second half portion, and reads out the contents of the ROM (201) for the forward direction of the time axis at the first half portion, and for the backward direction of the time axis at the second half portion.

Claim 12

The circuit of claim 11, wherein the D/A converter (3i, 3q) converts the digital signal received from the low pass filter (20) to an analog signal by a time division process.

Claim 13

A quadrature modulation circuit including at least one low pass filter (20) for limiting the frequency band-width of the base-band signal to be frequency-modulated, an adder (14) connected to the output of the low pass filter (20), a latch circuit (15) connected to the output of the adder (14) and one input of the adder (14) for adding the output of the adder (14) to the preceding output of the adder (14), a COS ROM (16) and a SIN ROM (17) for converting the phase value of the output from the adder (14) to an in-phase channel (1i) signal and a quadrature channel signal (1q) respectively, D/A converters (3i, 3q) for converting the digital signal received from the COS ROM (16) or SIN ROM (17) respectively, at least one filter (4i, 4q) for suppressing the aliases output from the D/A converter (3i, 3q), a quadrature modulator (5) for modulating (9) carrier signal with the output from the filter (4i, 4q): wherein the low pass filter (20) uses one symbol data in a set of symbol data as a sign data, and inverts the sign of the remaining symbol data and an output data from a ROM (2010) by using the one symbol data.

Claim 14

A quadrature modulation circuit including at least one low pass filter (20) using ROM for limiting the frequency band-width of the base-band signal to be frequency-modulated, an adder (14) connected to the output of the low pass filter (20), a latch circuit (15) connected to the output of the adder (14) and one input of the adder (14) for adding the output of the adder (14) to the preceding output of the adder (14), a COS ROM (16) and a SIN ROM (17) for converting the phase value of the output from the adder (14) to an in-phase channel signal (1i) and a quadrature channel signal (1q) respectively, D/A converters (3i, 3q) for converting the digital signal received from the COS ROM (16) or SIN ROM (17) respectively, at least one filter (4i, 4q) for suppressing the aliases output from the D/A converter (3i, 3q), a quadrature modulator (5) for modulating the output from the filter (4i, 4q): wherein the low pass filter (20) divides the data into a first half portion and a second half portion, and reads out the contents of the ROM (2011) for the forward direction of the time axis at the first half portion, and for the backward direction of the time axis at the second half portion.