Patent EP0492433A2 successfully refreshed from Google Patents.
EP0492433A2
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EP
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Method for placing a frequency synthesizer into standby mode and apparatus therefor
Assignee: Motorola Solutions Inc
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Filing: 1991-12-19
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Granted: —
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Expires: 2011-12-19
Abstract
Abstract A synthesizer (30) is placed in standby mode when a standby portion of a control register (47) is set. Once standby is activated, any detectors (33, 33') and counters (42, 43, 44) are inhibited. The inputs and outputs are reconfigured so as to minimize current drain and to stabilize the VCO (12) control voltage. Recovery from standby is accomplished in two phases. The first phase is started by the receipt of a terminate standby signal. This enables the inputs and starts the counters (42, 43, 44). The second phase is activated when a signal is received from a feedback counter (43) indicating it has completed a cycle. This causes the preset data to be loaded into the reference counter (44). The counters (42, 43, 44) are then synchronized; the detector (33) is initialized; and the detector (33) output is enabled. The device (30) also controls an output lock detector (55) and reference frequency signal during the standby mode. The system (30) is also compatible with variable modulus prescalers (11).
Inventors
- 👤 David C. Babin
- 👤 John D. Hatchett
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 10:42
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/199; H03L7/08; H03L7/0802; H03L2207/00; H03L2207/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
117 words
A method for operating a frequency synthesiser (30) of a phase locked loop having a standby mode, the method including bringing the frequency synthesizer out of standby mode comprising the steps of: enabling the receipt of a reference signal at a reference input of said frequency synthesizer (30) and a feedback signal at a feedback input of said frequency synthesizer (30); enabling the counting of a reference counter (44) of said frequency synthesizer (30) in response to said reference signal and a feedback counter (43) of said frequency synthesizer (30) in response to said feedback signal; synchronizing said feedback counter (43); starting said reference counter (44); and initializing a phase detector (33) of said frequency synthesizer (30).
Claim 2
Dependent Claim
57 words
The method of claim 1 wherein said step of synchronizing said feedback counter (43) comprises the steps of: receiving a signal at a standby logic means (48) for controlling said frequency synthesizer (30), said signal being received from said feedback counter (43); and loading a preset data from a reference register (45) into said reference counter (44).
Claim 3
Dependent Claim
47 words
The method of claim 1 or 2 further comprising the step of: receiving a terminate standby signal at a control logic means (46) for controlling data input to said frequency synthesizer (30); and storing said terminate standby signal in a control register (47) of said frequency synthesizer.
Claim 4
Independent Claim
119 words
The method of any of claims 1 to 3, including placing the frequency synthesizer (30) into standby mode comprising the steps of: setting an output of the phase detector (33) of said synthesizer (30) to a high impedance state; inhibiting the counting of the reference counter (44) of said frequency synthesizer (30) in response to a reference signal and the feedback counter (43) of said frequency synthesizer (30) in response to a feedback signal; maintaining a preset data in each of a reference register (45) coupled to said reference counter (44) and a feedback register (41) coupled to said feedback counter (43); and inhibiting said reference signal and said feedback signal from being received at said frequency synthesizer (30).
Claim 5
Dependent Claim
44 words
The method of claim 4 further comprising the step of: receiving a standby signal at a control logic means (46) for controlling data input to said frequency synthesizer (30); and storing said standby signal in a control register (47) of said frequency synthesizer (30).
Claim 6
Dependent Claim
30 words
The method of claim 4 or 5 further comprising the step of setting an output of a second phase detector (33') of said synthesizer (30) to a high logic level.
Claim 7
Dependent Claim
29 words
The method of claim 4, 5 or 6, further comprising the step of setting an output of a lock detector (55) of said synthesizer (30) to a static state.
Claim 8
Independent Claim
27 words
The method of any of claims 4 to 7 further comprising the step of inhibiting a reference input signal from being transmitted to said reference counter (44).
Claim 9
Dependent Claim
123 words
A freqency synthesiser (30) for a phase locked loop, including : a first counter (44) for receiving a frequency reference signal and providing an output signal (fr') to a standby logic means (48) and a phase detector (33); a second counter (43) for receiving a loop feedback signal (fin) and providing an output signal (fv') to the standby logic means and the phase detector; a first register (45) and a second register (41) respectively associated with the first and second counters for storing preset data; the arrangement being such that when the loop comes out of standby mode, the first and second counters are enabled and their outputs are synchronised by the standby logic means prior to enabling operation of the phase detector.
Claim 10
Dependent Claim
517 words
A synthesizer as claimed in claim 9 having a data input, a reference input, a feedback input, and an output, said synthesizer (30) comprising: control means (46) for receiving a control signal for said synthesizer (30), said control means (46) having an input coupled to said data input of said synthesizer (30) and an output; first register means (47) for storing data, said first register means (47) having an input coupled to said output of said control means (46) and an output; standby logic means (48) for controlling said synthesizer (30) in entering a standby mode and in terminating said standby mode, said standby logic means (48) having a first input coupled to said output of said first register means (47), a second input, a third input, a fourth input coupled to said feedback input, a first control output, a second control output, a reference output, and a feedback output; phase detector means (33) for detecting differences in a reference signal and a feedback signal, said phase detector means (33) having an output coupled to an output of said synthesizer (30), a control input coupled to said first control output of said standby logic means (48), a reference input coupled to said reference output of said standby logic means (48), and a feedback input coupled to said feedback output of said standby logic means (48); first counter means (44) for sequentially counting in response to an input reference signal, said first counter means (44) having a reference input coupled to said reference input of said synthesizer (30), a data input, and an output coupled to said second input of said standby logic means (48); buffer means (45) for storing data, said buffer means (45) having a data input coupled to said output of said control means (46) and a data output coupled to said data input of said first counter means (44); second register means (41) for storing data, said second register means (41) having a data input coupled to said output of said control means (46), a first output, and a second output; second counter means (42) for sequentially counting in response to an input signal, said second counter means (42) having a first input coupled to said first output of said second register means (41), a second input coupled to said feedback input of said synthesizer (30), and an output; third counter means (43) for sequentially counting in response to an input signal, said third counter means (43) having a first input coupled to said second output of said second register means (41), a second input coupled to said feedback input of said synthesizer (30), a first output, and a second output coupled to said third input of said standby logic means (48); and modulus control logic means (54) for controlling a prescaler, said modulus control logic means (54) having a first input coupled to said output of said second counter means (42), a second input coupled to said first output of said third counter means (43), a third input coupled to said second control output of said standby logic means (48), and an output.
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