A flexible redundancy architecture and fuse download scheme

Claim 2

The integrated circuit (100) of claim 1, wherein said first means produces a first set of signals (9, FL8-FL16) representing said specific selection signal for said faulty one of said first plurality of circuit elements, and a second set of signals (4, FL1-FL4) for selecting said one of said redundant circuit elements to be substituted for said faulty one of said first plurality of circuit elements.

Claim 3

The integrated circuit (100) of claim 2, wherein each of said plurality of redundant circuit elements has a redundant decoder (70(ML), 70(i)) that receives selection signals (ROW ADD BIT) from a source external to said integrated circuit and compares them to said first set of signals from said first means.

Claim 4

The integrated circuit (100) of claim 2 or 3, wherein said second set of signals from said first means enables a selected one of said redundant decoders of said plurality of redundant circuit elements.

Claim 5

The integrated circuit (100) according to any one of claims 2 to 4, further comprising: bus means (30B, 30C) for transmitting said first and second set of signals from said first means to said redundant decoders of said plurality of redundant circuit elements, preferably said first and second set of signals from said first means being multiplexed on said bus means.

Claim 6

In an integrated circuit (100) comprising a first plurality of circuit elements (MEMORY MACRO n, ARRAY) providing given circuit functions in response to specific enable signals, and a plurality of redundant circuit elements (REDUNDANCY), a method of setting selected ones of said plurality of redundant circuit elements so that they may be substituted for faulty ones of said first plurality of circuit elements when said specific enable signals are received, comprising the steps of: selecting discrete ones of said plurality of redundant circuit elements when the integrated circuit is first powered up; providing a first set of signals (9, FL8-FL16) to each of said discrete ones of said plurality of redundant circuit elements as they are selected, said first set of signals indicating the identity of the faulty ones of said first plurality of circuit elements to be replaced; and replacing said faulty ones of said first plurality of circuit elements with said selected ones of said plurality of redundant circuit elements when said specific enable signals are received.

Claim 7

The method of claim 6, wherein said integrated circuit further comprises a plurality of banks (10, 15) of nonvolatile storage elements.

Claim 8

The method of claim 7, wherein at least some of said plurality of fuse banks each store a discrete one of said first set of signals and a discrete one of a second set of signals.

Claim 9

The method of claim 8, wherein said second set of signals indicate which of said plurality of redundant circuit elements are to receive said first set of signals stored within the same one of said plurality of fuse banks.

Claim 10

In an integrated circuit (100) comprising a plurality of circuit elements (MEMORY MACRO n, ARRAY), some of which may be faulty, which respond to a discrete set of access signals, and a plurality of redundant elements (REDUNDANCY) that are programmed to respond to said discrete set of access signals to substitute for faulty ones of said plurality of circuit elements, a redundancy programming method comprising the steps of: testing said integrated circuit to determine which of said plurality of circuit elements are faulty; programming a plurality of sets of non-volatile storage elements (10, 10A, 10B, 15, 15A, 15Z), such that at least some of said plurality of sets of non-volatile storage elements store a first plurality of signals (9, FL8-FL16) that simulate the discrete set of access signals corresponding to a faulty one of said plurality of circuit elements and a second plurality of signals (4, FL1-FL4) indicating a selected one of said plurality of redundant elements to be substituted for said faulty one of said plurality of circuit elements; and sequentially downloading programmed ones of said plurality of sets of nonvolatile storage elements to set selected ones of said plurality of redundant elements to substitute for faulty ones of said plurality of circuit elements when said discrete set of access signals for faulty ones of said plurality of circuit elements are received.

Claim 11

A redundancy system for a memory chip (100) having a plurality of memory cells (MEMORY MACRO n, ARRAY) arranged in a plurality of rows, comprising: a plurality of rows of redundant memory cells (REDUNDANCY); a plurality of sets of nonvolatile storage elements, e.g. sets of fuses (10, 10A, 10B, 15, 15A, 15Z), each set comprising a first group (Fuse 1-7) of storage elements and a second group (Fuse 8-10) of storage elements; access means, e.g. a fuse downloader (L, Pj, SRj, 11A, 11B, 15A, 15B, 16), for accessing at least one of said plurality of sets of nonvolatile storage elements, said access means accessing said first group of storage elements for selecting one of said plurality of rows of redundant memory cells, and accessing said second group of storage elements for programming said selected one of said plurality of rows of redundant memory cells to substitute for a faulty one of said plurality of rows of memory cells.

Claim 12

The redundancy system as recited in claim 11, wherein said access means includes a first means (Pj, SRj) for serially accessing all of said plurality of sets of nonvolatile storage elements.

Claim 13

The redundancy system as recited in claim 12, wherein said first means comprises a shift register (SRj), wherein each element of said shift register produces an enable signal (Sj) that accesses a given one of said plurality of sets of nonvolatile storage elements when an enable bit is shifted thereto.

Claim 14

The redundancy system as recited in claim 12 or 13, wherein said access means further includes a second means, e.g. a data/control bus (30B, 30C), for bussing information from each of said plurality of sets of nonvolatile storage elements accessed by said first means to said plurality of rows of redundant memory cells.

Claim 15

The redundancy system as recited in claim 14, further comprising a third means (20A, 20C, 30A) for controlling said second means so that when a given one of said plurality of sets of nonvolatile storage elements is accessed, signals from said first group of storage elements are transmitted on said second means during a first download cycle, and signals from said second group of storage elements are accessed during a second download cycle.

Claim 16

The redundancy system according to any one of claims 11 to 15, wherein said plurality of rows of redundant memory cells is greater in number than said plurality of sets of nonvolatile storage elements.

Claim 17

The redundancy system according to any one of claims 11 to 16, wherein each of said plurality of sets of nonvolatile storage elements further includes a first nonvolatile storage element indicating that the particular set of nonvolatile storage elements has been programmed.

Claim 18

The redundancy system according to any one of claims 11 to 17, wherein each of said plurality of sets of nonvolatile storage elements further includes a second nonvolatile storage element indicating that the particular set of nonvolatile elements is faulty.

Claim 19

The redundancy system of claims 17 or 18, wherein said access means includes means to bypass further accessing of a given one of said plurality of sets of nonvolatile storage elements should either of its first or second nonvolatile storage elements indicate that access should be discontinued.

Claim 20

The redundancy system according to any one of claims 11 to 19, wherein said plurality of rows of redundant elements are arranged into groups, and wherein said first plurality of nonvolatile storage elements includes a first subset (Fuse 1-4) of nonvolatile storage elements which store logic signals (FL1-FL4) that select which group of said plurality of rows of redundant elements, and a second subset (Fuse 5-7) of nonvolatile storage elements which store logic signals (FL5-FL7) that select one of said plurality of rows of redundant elements within said selected group.

Claim 21

The redundancy system of claim 20, wherein said access means accesses the first subset of nonvolatile storage elements in a first download cycle, said second subset of nonvolatile storage elements in a second download cycle, and said second plurality of nonvolatile storage elements in a third download cycle.

Claim 22

The redundancy system according to any one of claims 11 to 21, wherein during access of a given one of said plurality of sets of nonvolatile storage elements, logic states from said first plurality of nonvolatile storage elements are transmitted on a control portion of said second means, and logic states from said second plurality of nonvolatile storage elements are transmitted on a data portion of said second means separate from said control portion of said second means.