Process for making planarized sub-micrometric trenches in integrated circuits

Claim 1

Process for obtaining planarized sub-micrometric trenches in integrated circuits accomplished with ULSI technology, comprising the sequential formation, on a silicon substrate (1), of a lower layer (2) of silicon oxide, of an intermediate layer (3) of silicon nitride and of an upper layer (4) of silicon oxide or of polycrystalline silicon, the etching of said layers (2, 3, 4) with the terminal point on the substrate (1), the etching of the substrate (1) for the accomplishment of a trench (8), the oxidation of the walls of the trench (8) and its filling with planarization dielectric material, characterized in that the etching of said layers (2, 3, 4) is initially limited to the opening of a window (5, 16) in said upper layer (4) and is followed by the formation of a further layer (6) of silicon oxide, which at said window (5, 16) forms a U-shaped cavity (7, 14, 18) having a width that is smaller than that of said window (5, 16), and by an anisotropic etching of said further layer (6) of oxide, of said layer of nitride (3) and of said lower layer (2) of oxide at said U-shaped cavity (7, 14, 18) so as to uncover a corresponding portion (10) of the substrate (1) having a smaller width than the initial window (5, 16) and equal to that of the desired trench (8).