Patent EP0490240A2 successfully refreshed from Google Patents.
EP0490240A2
Expired / Lapsed
EP
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Ferroelectric capacitor and method for forming local interconnection
Assignee: Micron Technology Inc
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Filing: 1991-12-03
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Granted: —
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Expires: 2011-12-03
Abstract
Abstract Problems arise when connecting the bottom plate of a ferroelectric capacitor to the source of its associated access transistor during the fabrication of an ultra large scale integrated memory circuit. The temperature and ambient of certain steps of the fabrication process adversely affects ohmic properties of the connection. To overcome these problems, an insulative layer is formed between the bottom plate of a ferroelectric capacitor and its associated transistor. The insulative layer separates the source from the bottom electrode, and subsequent high temperature swings during the remainder of the fabrication process do not produce any direct connection between the source and the bottom plate. After the memory circuits have been fabricated on the semiconductor wafer, a voltage is applied across the ferroelectric capacitor and the insulative layer, preferably during a wafer probe. The magnitude of the applied voltage is selected to breakdown the insulative layer, but does not damage the ferroelectric layer. As a result, a good ohmic contact is produced between the bottom plate and the source of its associated transistor.
Inventors
- 👤 Alfred P. Gnadinger
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:11
CPC Classifications
H; H10; H10B; H10B53/00
Claims Analysis
Total Claims: 58
Claim 1
Independent Claim
95 words
A semiconductor memory cell, comprising: a transistor having at least one diffused region, said transistor being adapted to be coupled to an associated bit line and an associated word line; a storage capacitor having a bottom electrode and a top electrode, said top electrode being separated from said bottom electrode by a layer of ferroelectric material disposed therebetween, and said top electrode being adapted to be coupled to a plate line; and an insulative layer disposed between said diffused region and said bottom electrode, said insulative layer separating said diffused region from said bottom electrode.
Claim 2
Dependent Claim
44 words
The memory cell, as set forth in claim 1, wherein said insulative layer has a first predetermined breakdown voltage, and said layer of ferroelectric material has a second preselected breakdown voltage, said second preselected breakdown voltage being greater than said first preselected breakdown voltage.
Claim 3
Dependent Claim
40 words
The memory cell, as set forth in claim 1, wherein said insulative layer has a first preselected thickness, and said layer of ferroelectric material has a second preselected thickness, said second preselected thickness being greater than said first preselected thickness.
Claim 4
Dependent Claim
46 words
The memory cell, as set forth in claim 3, wherein said first preselected thickness corresponds to a first preselected breakdown voltage and said second preselected thickness corresponds to a second preselected breakdown voltage, said second preselected breakdown voltage being greater than said first preselected breakdown voltage.
Claim 5
Dependent Claim
29 words
The memory cell, as set forth in claim 3, wherein said second preselected thickness is in the range of 5 to 50 times thicker than said first preselected thickness.
Claim 6
Dependent Claim
27 words
The memory cell, as set forth in claim 5, wherein said first preselected thickness is about 100 angstroms and said second preselected thickness is about 2000 angstroms.
Claim 7
Dependent Claim
38 words
The memory cell, as set forth in claim 1, wherein said insulative material has a first dielectric constant, and said ferroelectric material has a second dielectric constant, said second dielectric constant being greater than said first dielectric constant.
Claim 8
Dependent Claim
27 words
The memory cell, as set forth in claim 7, wherein said second dielectric constant is at least two orders of magnitude greater than said first dielectric constant.
Claim 9
Dependent Claim
25 words
The memory cell, as set forth in claim 8, wherein said first dielectric constant is about 4 and said second dielectric constant is about 1000.
Claim 10
Dependent Claim
30 words
The memory cell, as set forth in claim 1, wherein said ferroelectric material is selected from a group consisting of lead zircronate titanate, lanthanum-doped lead zircronate titanate, or lithium niobate.
Claim 11
Dependent Claim
40 words
The memory cell, as set forth in claim 1, wherein said insulative layer is adapted to provide an ohmic contact between said diffused region and said bottom electrode in response to a preselected voltage being delivered across said insulative layer.
Claim 12
Dependent Claim
132 words
A semiconductor memory cell, comprising: an access transistor having a drain, a source and a gate, said drain being adapted to be coupled to an associated bit line and said gate being adapted to be coupled to an associated word line; a ferroelectric storage capacitor having a conductive bottom plate and a conductive top plate, said top plate being spaced a first preselected distance from said bottom plate and being connected to said bottom plate by a layer of ferroelectric material disposed therebetween, said top plate being adapted to be coupled to a plate line and said bottom plate being spaced from said source by a second preselected distance; and a layer of insulative material being disposed between said source and said bottom plate and connecting said source to said bottom plate.
Claim 13
Dependent Claim
42 words
The memory cell, as set forth in claim 12, wherein said insulative material has a first predetermined breakdown voltage, and said ferroelectric material has a second preselected breakdown voltage, said second preselected breakdown voltage being greater than said first preselected breakdown voltage.
Claim 14
Dependent Claim
62 words
The memory cell, as set forth in claim 13, wherein said layer of insulative material is adapted for breaking down and substantially connecting said bottom plate to said source in response to an application of a voltage having a magnitude greater than said first preselected breakdown voltage and less than said second preselected breakdown voltage between said source and said top plate.
Claim 15
Dependent Claim
40 words
The memory cell, as set forth in claim 12, wherein said insulative layer has a first preselected thickness, and said layer of ferroelectric material has a second preselected thickness, said second preselected thickness being greater than said first preselected thickness.
Claim 16
Dependent Claim
46 words
The memory cell, as set forth in claim 15, wherein said first preselected thickness corresponds to a first preselected breakdown voltage and said second preselected thickness corresponds to a second preselected breakdown voltage, said second preselected breakdown voltage being greater than said first preselected breakdown voltage.
Claim 17
Dependent Claim
26 words
The memory cell, as set forth in claim 15, wherein said second preselected thickness is about an order of magnitude thicker than said first preselected thickness.
Claim 18
Dependent Claim
27 words
The memory cell, as set forth in claim 17, wherein said first preselected thickness is about 100 angstroms and said second preselected thickness is about 2000 angstroms.
Claim 19
Dependent Claim
38 words
The memory cell, as set forth in claim 12, wherein said insulative material has a first dielectric constant, and said ferroelectric material has a second dielectric constant, said second dielectric constant being greater than said first dielectric constant.
Claim 20
Dependent Claim
27 words
The memory cell, as set forth in claim 19, wherein said second dielectric constant is at least two orders of magnitude greater than said first dielectric constant.
Claim 21
Dependent Claim
25 words
The memory cell, as set forth in claim 20, wherein said first dielectric constant is about 4 and said second dielectric constant is about 1000.
Claim 22
Dependent Claim
30 words
The memory cell, as set forth in claim 12, wherein said ferroelectric material is selected from a group consisting of lead zircronate titanate, lanthanum-doped lead zircronate titanate, or lithium niobate.
Claim 23
Dependent Claim
39 words
The memory cell, as set forth in claim 12, wherein said insulative layer is adapted to provide an ohmic contact between said source and said bottom plate in response to a preselected voltage being delivered across said insulative layer.
Claim 24
Dependent Claim
234 words
A semiconductor memory cell, comprising: a MOSFET access transistor having a drain, a source, and a gate, said drain being connected to an associated bit line and said gate being connected to an associated word line; a ferroelectric storage capacitor having a conductive top plate having a top and bottom surface, the top surface of said top plate being connected to a plate line, and a conductive bottom plate having a top and bottom surface, the bottom surface of said top plate being spaced a first preselected distance from the top surface of said bottom plate and the bottom surface of said bottom plate being spaced from said source by a second preselected distance, the bottom surface of said top plate being connected to the top surface of said bottom plate by a layer of ferroelectric material disposed therebetween, said ferroelectric layer having a thickness substantially equal to said first preselected distance; and an insulative layer being disposed between said source and the bottom surface of said bottom plate and connecting said source to the bottom surface of said bottom plate, said insulative layer having a thickness substantially equal to said second preselected distance, the relative thicknesses of said ferroelectric layer and of said insulative layer being selected to provide breakdown of only said insulative layer in response to a voltage having a predetermined magnitude applied between said plate line and said bit line.
Claim 25
Independent Claim
71 words
A method of fabricating a memory cell on a semiconductor wafer, comprising the steps of: (a) forming an access transistor having a source, a drain, and a gate; (b) applying a layer of insulative material onto said source; (c) forming a first conductive layer over said insulative layer; (d) applying a layer of ferroelectric material onto said first conductive layer; and (e) forming a second conductive layer over said ferroelectric layer.
Claim 26
Dependent Claim
27 words
The method, as set forth in claim 25, wherein step (b) comprises the step of applying a first preselected thickness of said insulative material onto said source.
Claim 27
Dependent Claim
40 words
The method, as set forth in claim 26, wherein step (d) comprises the step of applying a second preselected thickness of said ferroelectric material onto said first conductive layer, said second preselected thickness being greater than said first preselected thickness.
Claim 28
Dependent Claim
46 words
The method, as set forth in claim 25, further comprising the step of: delivering a voltage between said source and said second conductive layer, said voltage having a magnitude sufficient to breakdown said layer of insulative material and insufficient to breakdown said layer of ferroelectric material.
Claim 29
Independent Claim
122 words
A method of fabricating a memory cell on a semiconductor wafer, comprising the steps of: forming an access transistor having a source, a drain, and a gate; applying a layer of insulative material having a first preselected breakdown voltage onto said source; depositing a first conductive layer onto said insulative layer; applying a layer of ferroelectric material having a second preselected breakdown voltage onto said first conductive layer, said second preselected breakdown voltage being greater than said first preselected breakdown voltage; depositing a second conductive layer onto said ferroelectric layer; and delivering a voltage between said source and said second conductive layer, said voltage having a magnitude greater than said first preselected breakdown voltage and less than said second preselected breakdown voltage.
Claim 30
Independent Claim
130 words
A method of fabricating a memory cell on a semiconductor wafer, comprising the steps of: forming an access transistor having a source, a drain, and a gate; applying an insulative layer having a first preselected thickness corresponding to a first preselected breakdown voltage onto said source; depositing a first conductive layer onto said insulative layer; applying a ferroelectric layer having a second preselected thickness corresponding to a second preselected breakdown voltage onto said first conductive layer, said second preselected breakdown voltage being greater than said first preselected breakdown voltage; depositing a second conductive layer onto said ferroelectric layer; and delivering a voltage between said source and said second conductive layer, said voltage having a magnitude greater than said first preselected breakdown voltage and less than said second preselected breakdown voltage.
Claim 31
Independent Claim
126 words
A method of fabricating a memory cell, comprising the steps of: depositing silicon dioxide onto a semiconductor wafer; removing selected portions of said silicon dioxide to uncover selected portions of said semiconductor wafer; diffusing impurities into said uncovered selected portions of said semiconductor wafer to form a source and a drain of a transistor; applying an insulative layer having a first preselected thickness corresponding to a first preselected breakdown voltage onto said source; depositing a first conductive layer onto said insulative layer; applying a ferroelectric layer having a second preselected thickness corresponding to a second preselected breakdown voltage onto said first metallic layer, said second preselected breakdown voltage being greater than said first preselected breakdown voltage; and depositing a second conductive layer onto said ferroelectric layer.
Claim 32
Dependent Claim
44 words
The method, as set forth in claim 31, further comprising the step of: delivering a voltage between said source and said second conductive layer, said voltage having a magnitude greater than said first preselected breakdown voltage and less than said second preselected breakdown voltage.
Claim 33
Dependent Claim
103 words
A semiconductor memory cell, comprising: a transistor having at least one diffused region, said transistor being adapted to be coupled to an associated bit line and an associated word line; a polysilicon layer disposed on said diffused region; a storage capacitor having a bottom electrode and a top electrode, said top electrode being separated from said bottom electrode by a layer of ferroelectric material disposed therebetween, and said top electrode being adapted to be coupled to a plate line; and an insulative layer disposed between said polysilicon layer and said bottom electrode, said insulative layer separating said polysilicon layer from said bottom electrode.
Claim 34
Dependent Claim
44 words
The memory cell, as set forth in claim 33, wherein said insulative layer has a first predetermined breakdown voltage, and said layer of ferroelectric material has a second preselected breakdown voltage, said second preselected breakdown voltage being greater than said first preselected breakdown voltage.
Claim 35
Dependent Claim
40 words
The memory cell, as set forth in claim 33, wherein said insulative layer has a first preselected thickness, and said layer of ferroelectric material has a second preselected thickness, said second preselected thickness being greater than said first preselected thickness.
Claim 36
Dependent Claim
46 words
The memory cell, as set forth in claim 35, wherein said first preselected thickness corresponds to a first preselected breakdown voltage and said second preselected thickness corresponds to a second preselected breakdown voltage, said second preselected breakdown voltage being greater than said first preselected breakdown voltage.
Claim 37
Dependent Claim
29 words
The memory cell, as set forth in claim 35, wherein said second preselected thickness is in the range of 5 to 50 times thicker than said first preselected thickness.
Claim 38
Dependent Claim
27 words
The memory cell, as set forth in claim 37, wherein said first preselected thickness is about 100 angstroms and said second preselected thickness is about 2000 angstroms.
Claim 39
Dependent Claim
38 words
The memory cell, as set forth in claim 33, wherein said insulative material has a first dielectric constant, and said ferroelectric material has a second dielectric constant, said second dielectric constant being greater than said first dielectric constant.
Claim 40
Dependent Claim
27 words
The memory cell, as set forth in claim 39, wherein said second dielectric constant is at least two orders of magnitude greater than said first dielectric constant.
Claim 41
Dependent Claim
25 words
The memory cell, as set forth in claim 40, wherein said first dielectric constant is about 4 and said second dielectric constant is about 1000.
Claim 42
Dependent Claim
30 words
The memory cell, as set forth in claim 33, wherein said ferroelectric material is selected from a group consisting of lead zircronate titanate, lanthanum-doped lead zircronate titanate, or lithium niobate.
Claim 43
Dependent Claim
40 words
The memory cell, as set forth in claim 33, wherein said insulative layer is adapted to provide an ohmic contact between said polysilicon layer and said bottom electrode in response to a preselected voltage being delivered across said insulative layer.
Claim 44
Dependent Claim
142 words
A semiconductor memory cell, comprising: an access transistor having a drain, a source and a gate, said drain being adapted to be coupled to an associated bit line and said gate being adapted to be coupled to an associated word line; a polysilicon layer disposed on said source; a ferroelectric storage capacitor having a conductive bottom plate and a conductive top plate, said top plate being spaced a first preselected distance from said bottom plate and being connected to said bottom plate by a layer of ferroelectric material disposed therebetween, said top plate being adapted to be coupled to a plate line and said bottom plate being spaced from said polysilicon layer by a second preselected distance; and a layer of insulative material being disposed between said polysilicon layer and said bottom plate and connecting said polysilicon layer to said bottom plate.
Claim 45
Dependent Claim
42 words
The memory cell, as set forth in claim 44, wherein said insulative material has a first predetermined breakdown voltage, and said ferroelectric material has a second preselected breakdown voltage, said second preselected breakdown voltage being greater than said first preselected breakdown voltage.
Claim 46
Dependent Claim
63 words
The memory cell, as set forth in claim 45, wherein said layer of insulative material is adapted for breaking down and substantially connecting said bottom plate to said polysilicon layer in response to an application of a voltage having a magnitude greater than said first preselected breakdown voltage and less than said second preselected breakdown voltage between said source and said top plate.
Claim 47
Dependent Claim
40 words
The memory cell, as set forth in claim 44, wherein said insulative layer has a first preselected thickness, and said layer of ferroelectric material has a second preselected thickness, said second preselected thickness being greater than said first preselected thickness.
Claim 48
Dependent Claim
46 words
The memory cell, as set forth in claim 47, wherein said first preselected thickness corresponds to a first preselected breakdown voltage and said second preselected thickness corresponds to a second preselected breakdown voltage, said second preselected breakdown voltage being greater than said first preselected breakdown voltage.
Claim 49
Dependent Claim
38 words
The memory cell, as set forth in claim 44, wherein said insulative material has a first dielectric constant, and said ferroelectric material has a second dielectric constant, said second dielectric constant being greater than said first dielectric constant.
Claim 50
Dependent Claim
27 words
The memory cell, as set forth in claim 49, wherein said second dielectric constant is at least two orders of magnitude greater than said first dielectric constant.
Claim 51
Dependent Claim
25 words
The memory cell, as set forth in claim 50, wherein said first dielectric constant is about 4 and said second dielectric constant is about 1000.
Claim 52
Dependent Claim
30 words
The memory cell, as set forth in claim 44, wherein said ferroelectric material is selected from a group consisting of lead zircronate titanate, lanthanum-doped lead zircronate titanate, or lithium niobate.
Claim 53
Independent Claim
81 words
A method of fabricating a memory cell on a semiconductor wafer, comprising the steps of: (a) forming an access transistor having a source, a drain, and a gate; (b) depositing a layer of polysilicon onto said source; (c) applying a layer of insulative material onto said polysilicon layer; (d) forming a first conductive layer over said insulative layer; (e) applying a layer of ferroelectric material onto said first conductive layer; and (f) forming a second conductive layer over said ferroelectric layer.
Claim 54
Dependent Claim
28 words
The method, as set forth in claim 53, wherein step (c) comprises the step of applying a first preselected thickness of said insulative material onto said polysilicon layer.
Claim 55
Dependent Claim
40 words
The method, as set forth in claim 54, wherein step (e) comprises the step of applying a second preselected thickness of said ferroelectric material onto said first conductive layer, said second preselected thickness being greater than said first preselected thickness.
Claim 56
Dependent Claim
47 words
The method, as set forth in claim 53, further comprising the step of: (g) delivering a voltage between said source and said second conductive layer, said voltage having a magnitude sufficient to breakdown said layer of insulative material and insufficient to breakdown said layer of ferroelectric material.
Claim 57
Independent Claim
131 words
A method of fabricating a memory cell on a semiconductor wafer, comprising the steps of: forming an access transistor having a source, a drain, and a gate; depositing a layer of polysilicon onto said source; applying a layer of insulative material having a first preselected breakdown voltage onto said polysilicon layer; depositing a first conductive layer onto said insulative layer; applying a layer of ferroelectric material having a second preselected breakdown voltage onto said first conductive layer, said second preselected breakdown voltage being greater than said first preselected breakdown voltage; depositing a second conductive layer onto said ferroelectric layer; and delivering a voltage between said source and said second conductive layer, said voltage having a magnitude greater than said first preselected breakdown voltage and less than said second preselected breakdown voltage.
Claim 58
Independent Claim
139 words
A method of fabricating a memory cell on a semiconductor wafer, comprising the steps of: forming an access transistor having a source, a drain, and a gate; depositing a layer of polysilicon onto said source; applying an insulative layer having a first preselected thickness corresponding to a first preselected breakdown voltage onto said polysilicon layer; depositing a first conductive layer onto said insulative layer; applying a ferroelectric layer having a second preselected thickness corresponding to a second preselected breakdown voltage onto said first conductive layer, said second preselected breakdown voltage being greater than said first preselected breakdown voltage; depositing a second conductive layer onto said ferroelectric layer; and delivering a voltage between said source and said second conductive layer, said voltage having a magnitude greater than said first preselected breakdown voltage and less than said second preselected breakdown voltage.
References Cited (Backward Citations)
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