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EP0488893A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method and device for conveying binary differential signals and application in carry select adders

Assignee: Bull SAS
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Filing: 1991-11-27
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Granted: —
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Expires: 2011-11-27
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Abstract

Abstract Translated from French L'invention se situe dans le domaine des transferts de signaux électriques de type différentiel. Afin d'accélérer ce transfert indépendamment des dispersions de fabrication, notamment dans les réalisations sous forme de circuit intégré, l'invention concerne un procédé pour transférer une information binaire de type différentiel présente sur deux premières lignes de bit (e, e*) vers deux secondes lignes de bit (s, s*) par l'intermédiaire d'un amplificateur différentiel (A), ledit procédé comportant une phase de précharge suivie d'une phase d'évaluation desdites premières lignes de bit, ledit procédé étant caractérisé en ce que ladite phase de précharge consiste à mettre en court-circuit lesdites premières lignes de bit entre elles et à mettre en court-circuit au moins une desdites secondes lignes de bit avec lesdites premières lignes de bit. L'invention concerne aussi un circuit pour la mise en oeuvre du procédé. Application notamment aux additionneurs à sélection de retenue. <IMAGE> The invention relates to the field of transfers of electrical signals of the differential type. In order to accelerate this transfer independently of the manufacturing dispersions, in particular in the embodiments in the form of an integrated circuit, the invention relates to a method for transferring binary information of differential type present on the first two bit lines (e, e *) to two second bit lines (s, s *) via a differential amplifier (A), said method comprising a precharge phase followed by an evaluation phase of said first bit lines, said method being characterized in that said precharging phase consists in short-circuiting said first bit lines therebetween and in short-circuiting at least one of said second bit lines with said first bit lines. The invention also relates to a circuit for implementing the method. Application in particular to adders with retention selection. <IMAGE>

Inventors

  • 👤 Georges Neu

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 03:47
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/507; G11; G11C; G11C7/00; G11C7/12; H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; H03K5/249

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

DE2317497B1 Cited
US4634890A Cited
EP0264933A2 Cited
US4932002A Cited

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