Sense amplifier circuit implemented by bipolar transistor and improved in current consumption

Assignee: NEC Corp

•

Filing: 1991-11-28

•

Granted: —

•

Expires: 2011-11-28

📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A differential amplifier circuit comprises a differential amplifier (24a1) responsive to an input differntial voltage signal and implemented by a parallel combination of first and second bipolar transistors (Q11/Q12) asoicated with a first constant current source (Ia1), a pair of interconnections (24b) coupled with the collector nodes of the first and second bipolar transistors, a current-to-voltage converter (24c) having a series of a resistor (R11) and a third bipolar transistor (Q13) associated with the first bipolar transistor and a series of a resistor (R12) and a fourth bipolar transistor (Q14) associated with the second bipolar transistor, and a standby current source (24e) coupled between the third and fourth bipolar transistors and a ground voltage line, and branch currents from the first and second bipolar transistors are inversely proportional to branch currents from the third and fourth bipolar transistors to the standby current source so that the third and fourth bipolar transistors drive the interconnections at high speed without sacrifice of current consumption. <IMAGE>

Inventors

👤 Hiroyuki Takahashi

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-07 05:11

CPC Classifications

G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416; G11C7/00; G11C7/06; G11C7/062

Claims Analysis

Total Claims: 5

Claim 1

Independent Claim 321 words

A sense amplifier circuit comprising: a) a differential amplifier circuit (24a1 to 24an) having first and second bipolar transistors (Q11/ Q12) controlled with an input differential voltage signal supplied to the base nodes thereof, and a first constant current source (Ia1) coupled between the emitter nodes of said first and second bipolar transistors and a first constant voltage source, and activated with an activation signal (ADY) for allowing first and second branch-currents to respectively pass through said first and second bipolar transistors, b) a pair of interconnections (24b) respectively coupled with the collector nodes of said first and second bipolar transistors, c) a current-to-voltage converting unit (24c) having a first series combination of a first resistive element (R11) and a third bipolar transistor (Q13) associated with said first bipolar transistor and coupled between a second constant voltage source ( Vcc) and one of said pair of interconnections, a second series combination of a second resistive element (R12) and a fourth bipolar transistor (Q14) associated with said second bipolar transistor and coupled between said second constant voltage source and the other of said pair of interconnections, and a third constant voltage source (Vct) coupled with the base nodes of said third and fourth bipolar transistors for producing an output differential voltage signal at the collector nodes of said third and fourth bipolar transistors; and d) a source of standby current (24e; 31a) associated with said first and second series combinations, characterized in that said source of standby current has a second constant current source (Ie; If) coupled with said first constant voltage source, and distributing means (D1/ D2; D3/ D4) coupled between said pair of interconnections and said second constant current source and operative to allow third and fourth branch-currents to flow from said third and fourth bipolar transistors to said second constant current source, said first and second branch currents being inversely proportional to said third and fourth branch currents, respectively.

Claim 2

Dependent Claim 55 words

A sense amplifier circuit as set forth in claim 1, in which said distributing means has a first diode element (D1; D3) coupled between said one of said interconnections and said second constant current source, and a second diode element (D2; D4) coupled between said other of said interconnections and said second constant current source.

Claim 3

Dependent Claim 31 words

A sense amplifier circuit as set forth in claim 2, in which both of said current-to-voltage converting unit and said distributing means are coupled with first ends (N11/N12) of said interconnections.

Claim 4

Dependent Claim 49 words

A sense amplifier circuit as set forth in claim 2, in which said current-to-voltage converting unit is coupled with first ends (N11/ N12) of said interconnections, and in which said distributing means is coupled with second ends of said interconnections, said first ends being opposite to said second ends.

Claim 5

Dependent Claim 92 words

A sense amplifier circuit as set forth in claim 2, in which said sense amplifier circuit further comprises e) an emitter follower circuit (41a) having fifth and sixth bipolar transistors (Q41/ Q42) coupled between said second constant voltage source and signal lines of an output data bus (24d) and controlled by the collector nodes of said third and fourth bipolar transistors, and f) a differential circuit (41b) having seventh and eighth bipolar transistors (Q43/ Q44) coupled between said signal lines and a third constant current source (Ig) and controlled by said interconnections.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag

Select Category

Notes (Optional)