Patent EP0488283A2 successfully refreshed from Google Patents.
EP0488283A2
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Method of fabricating memory cell for semiconductor integrated circuit
Assignee: NEC Corp
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Filing: 1991-11-28
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Granted: —
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Expires: 2011-11-28
Abstract
Abstract According to a method of fabricating a memory cell for a semiconductor integrated circuit, a lower electrode (6) having a predetermined shape is formed on a semiconductor layer. A first insulating interlayer (8) is formed on an entire surface of the semiconductor layer such that only a top surface of the lower electrode is exposed. A dielectric (10) having a high dielectric constant such as strontium titanate is formed on the lower electrode and on the semiconductor layer. An upper electrode (11) is formed on the dielectric having a high dielectric constant. The upper electrode constitutes a capacitor with the lower electrode through the dielectric.
Inventors
- 👤 Sakuma c/o NEC Corporation Toshiyuki
- 👤 Miyasaka c/o NEC Corporation Yoichi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 08:09
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
102 words
A method of fabricating a memory cell for a semiconductor integrated circuit, comprising the steps of: forming a lower electrode (6) having a predetermined shape on a semiconductor layer (4, 5); forming a first insulating interlayer (8) on an entire surface of said semiconductor layer such that only a top surface of said lower electrode is exposed; forming a dielectric (10) having a high dielectric constant on said lower electrode and on said semiconductor layer; and forming an upper electrode (11) on said dielectric having a high dielectric constant, said upper electrode constituting a capacitor with said lower electrode through said dielectric.
Claim 2
Dependent Claim
39 words
A method according to claim 1, wherein said lower electrode consists of polysilicon (6) on top of which a barrier metal (7) is stacked, and said first insulating interlayer is formed at the same level as said barrier metal.
Claim 3
Dependent Claim
44 words
A method according to claim 1, wherein a MOS transistor having diffusion regions (3) corresponding to a source and a drain and a gate arranged between said diffusion regions via an insulating film is formed on a semiconductor substrate (4) constituting said semiconductor layer.
Claim 4
Dependent Claim
46 words
A method according to claim 3, wherein a second insulating interlayer (5) is formed on said semiconductor substrate to cover said gate, and said lower electrode is formed on said second insulating interlayer so as to be connected to said diffusion regions of said semiconductor substrate.
Claim 5
Dependent Claim
42 words
A method according to claim 3, wherein a bit line (2) of said memory cell is formed on a surface of said semiconductor substrate so as to be in contact with said diffusion layers, and said gate constitutes a word line (1).
Claim 6
Independent Claim
89 words
A method of fabricating a memory cell for a semiconductor integrated circuit, comprising the steps of: forming a lower electrode (106) having a predetermined shape on a semiconductor layer (104, 105); forming a first insulating interlayer (108) only on side surfaces of said lower electrode; forming a dielectric (109) having a high dielectric constant on said lower electrode and said semiconductor layer; and forming an upper electrode (110) on said dielectric having a high dielectric constant, said upper electrode constituting a capacitor with said lower electrode through said dielectric.
Claim 7
Dependent Claim
44 words
A method according to claim 6, wherein a MOS transistor having diffusion regions (103) corresponding to a source and a drain and a gate arranged between said diffusion regions via an insulating film is formed on a semiconductor substrate (104) constituting said semiconductor layer.
Claim 8
Dependent Claim
46 words
A method according to claim 7, wherein a second insulating interlayer (105) is formed on said semiconductor substrate to cover said gate, and said lower electrode is formed on said second insulating interlayer so as to be connected to said diffusion regions on said semiconductor substrate.
Claim 9
Dependent Claim
42 words
A method according to claim 7, wherein a bit line (102) of said memory cell is formed on a surface of said semiconductor substrate so as to be in contact with said diffusion regions, and said gate constitutes a word line (101).
Claim 10
Independent Claim
83 words
A method of fabricating a memory cell for a semiconductor integrated circuit, comprising the steps of: forming a lower electrode (206) having a predetermined shape on a semiconductor layer (204); forming a dielectric (208) having a high dielectric constant on an entire surface of said semiconductor layer to have a predetermined thickness on said lower electrode; and forming an upper electrode (209) on said dielectric having a high dielectric constant, said upper electrode constituting a capacitor with said lower electrode through said dielectric.
Claim 11
Dependent Claim
44 words
A method according to claim 10, wherein a MOS transistor having diffusion regions (203) corresponding to a source and a drain and a gate arranged between said diffusion regions via an insulating film is formed on a semiconductor substrate (204) constituting said semiconductor layer.
Claim 12
Dependent Claim
46 words
A method according to claim 11, wherein a second insulating interlayer (205) is formed on said semiconductor substrate to cover said gate, and said lower electrode is formed on said second insulating interlayer so as to be connected to said diffusion regions on said semiconductor substrate.
Claim 13
Dependent Claim
42 words
A method according to claim 11, wherein a bit line (202) of said memory cell is formed on a surface of said semiconductor substrate so as to be in contact with said diffusion regions, and said gate constitutes a word line (201).
Claim 14
Dependent Claim
68 words
A method according to claim 10, wherein the step of forming said dielectric having a high dielectric constant comprises the steps of stacking said dielectric having a high dielectric constant to have a large thickness on the entire surface of said semiconductor layer, and processing said dielectric having a high dielectric constant by means of etching back so as to have a predetermined thickness on said lower electrode.
References Cited (Backward Citations)
No citation records indexed.
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