Patent EP0487819A2 successfully refreshed from Google Patents.
EP0487819A2
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EP
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Video random access memory with fast, alligned clear and copy
Assignee: International Business Machines Corp
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Filing: 1991-06-06
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Granted: —
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Expires: 2011-06-06
Abstract
Abstract A video random access memory (VRAM) includes a dynamic random access memory (DRAM) array and a serial access memory (SAM) connected to bi-directional random and serial ports. The SAM provides the capability for partial but aligned data transfer or mask write back of data from an external source for subsequent partial write operations in the DRAM array. These sources include color registers, on-chip arithmetic logic unit (ALU) output, or the random port. Partial but aligned transfers from the SAM to the DRAM array are accomplished by a data transfer into a selected row between two specified column addresses of the DRAM array. Alternatively, a masked write back into a row of the DRAM array is based on mask register contents. Improved serial access memory data input operation for DRAM array is accomplished by means of a source of "0s" or "1s" for a clear operation, providing a page mode fill from the RAM port or an on-chip ALU, and providing a color register load or based on random port input data. In addition, the use of a mask register for partial write back into a row also enhances serial access memory data input operations to the DRAM array. In one modification, a second SAM connected to a second bi-directional serial port is provided. The second SAM is connected to the first SAM to transfer data therebetween in parallel.
Inventors
- 👤 Matthew Elsner
- 👤 Satish Gupta
- 👤 Roderick Michael Peters West
- 👤 Todd Williams
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 22:14
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
146 words
In video random access memory of the type including a random access memory array, a bi-directional random port communicating with said random access memory array, a serial access memory connected to receive row data from said random access memory array and outputing serial data to a display device via a serial port, the improvement comprising: said serial port being bi-directional and said serial access memory being connected to said random access memory array to provide for partial but aligned data transfer or mask write back of data from an on-chip or external source for subsequent partial write operations in said random access memory array; and means for controlling partial but aligned transfers from said serial access memory to said random access memory array by a data transfer into an aligned update region between specified column addresses of a selected row of said random access memory array.
Claim 2
Dependent Claim
33 words
The video random access memory recited in claim 1 wherein said means for controlling partial but aligned transfers includes means connected to said serial access memory for specifying a range of column addresses.
Claim 3
Dependent Claim
91 words
The video random access memory recited in claim 1 or 2 wherein said video random access memory includes an address port for receiving address data, said improvement further comprising: serial access memory address buffer means connected to said address port for storing serial access memory address data; and address counter means connected to said serial access memory and responsive to said stored serial access memory address data for selecting addresses of said serial access memory corresponding to said specified column addresses of a selected row of said random access memory array.
Claim 4
Dependent Claim
109 words
The video random access memory recited in claim 3 wherein said video random access memory further includes sense amplifiers for reading data from said random access memory array to said bi-directional random port, said improvement further comprising: bi-directional multiplexer means connected between said serial access memory and said sense amplifiers and bi-directional serial port for establishing data input paths to said serial access memory from said sense amplifiers or said bi- directional serial port or an output from said serial access memory to said random port to said serial port; and multiplexer control means connected to said multiplexer means for selecting a data path and direction of data flow.
Claim 5
Dependent Claim
92 words
The video random access memory recited in claim 4 wherein said improvement further comprises: input buffer means connected to said random port for temporarily storing input data; latch means connected to said sense amplifiers for temporarily storing data read out of said random access memory array; arithmetic logic unit means connected to receive data temporarily stored in said input buffer means and latch means for modifying said data read out of said random access memory array; and means for reading said modified data into said serial access memory via said multiplexer means.
Claim 6
Dependent Claim
55 words
The video random access memory recited in claim 5 wherein said improvement further comprises operation code register means connected to said address port for receiving and temporarily storing an operation code, said arithmetic and logic unit means being responsive to said operation code for modifying said data read out of said random access memory array.
Claim 7
Dependent Claim
82 words
The video random access memory recited in claim 4 wherein said improvement further comprises: latch means connected to said sense amplifiers for temporarily storing data read out of said random access memory array; arithmetic logic unit means connected to receive data temporarily from said serial access memory via said multiplexer means and latch means for modifying said data read out of said random access memory array; and means for reading said modified data into said serial access memory via said multiplexer means.
Claim 8
Dependent Claim
55 words
The video random access memory recited in claim 7 wherein said improvement further comprises operation code register means connected to said address port for receiving and temporarily storing an operation code, said arithmetic and logic unit means being responsive to said operation code for modifying said data read out of said random access memory array.
Claim 9
Dependent Claim
106 words
The video random access memory recited in claim 4 wherein said improvement further comprises: input buffer means connected to said random port for temporarily storing input data; latch means connected to said sense amplifiers for temporarily storing data read out of said random access memory array; arithmetic logic unit means connected to receive data that is either temporarily stored in said input buffer means or from said serial access memory via said multiplexer means and said latch means for modifying said data read out of said random access memory array; and means for reading said modified data into said serial access memory via said multiplexer means.
Claim 10
Dependent Claim
55 words
The video random access memory recited in claim 9 wherein said improvement further comprises operation code register means connected to said address port for receiving and temporarily storing an operation code, said arithmetic and logic unit means being responsive to said operation code for modifying said data read out of said random access memory array.
Claim 11
Dependent Claim
42 words
The video random access memory recited in claim 4 wherein said improvement further comprises: color register means loaded from said bi-directional random port; and means for reading data from said color register means into said serial access memory via said multiplexer means.
Claim 12
Dependent Claim
41 words
The video random access memory recited in claim 4 wherein said improvement further comprises mask register means loaded from said bi-directional random port, data in said mask register means masking data read into said serial access memory via said multiplexer means.
Claim 13
Dependent Claim
43 words
The video random access memory recited in claim 3 wherein said improvement further comprises align register means connected to said serial access memory for controlling with said serial access memory address counter means a range of addresses addressed in said serial access memory.
Claim 14
Dependent Claim
52 words
The video random access memory recited in one of claims 1 to 13 further comprising: a second bi-directional serial port; and a second serial access memory connected to said second bi-directional serial port, said second serial access memory being connected to transfer data bi-directionally to or from said first serial access memory.
Claim 15
Dependent Claim
112 words
The video random access memory recited in claim 14 wherein said video random access memory further includes sense amplifiers for reading data from said random access memory array to said bi-directional random port, said improvement further comprising: bi-directional multiplexer means connected between said first serial access memory and said sense amplifiers and bi-directional serial port for establishing data input paths to said first serial access memory from said sense amplifiers or said bi- directional serial port or an output from said first serial access memory to said random port to said serial port; and multiplexer control means connected to said multiplexer means for selecting a data path and direction of data flow.
Claim 16
Dependent Claim
108 words
The video random access memory recited in claim 15 wherein said improvement further comprises: input buffer means connected to said random port for temporarily storing input data; latch means connected to said sense amplifiers for temporarily storing data read out of said random access memory array; arithmetic logic unit means connected to receive data that is either temporarily stored in said input buffer means or from said first serial access memory via said multiplexer means and said latch means for modifying said data read out of said random access memory array; and means for reading said modified data into said first serial access memory via said multiplexer means.
Claim 17
Dependent Claim
55 words
The video random access memory recited in claim 16 wherein said improvement further comprises operation code register means connected to said address port for receiving and temporarily storing an operation code, said arithmetic and logic unit means being responsive to said operation code for modifying said data read out of said random access memory array.
Claim 18
Dependent Claim
43 words
The video random access memory recited in claim 15 wherein said improvement further comprises: color register means loaded from said bi-directional random port; and means for reading data from said color register means into said first serial access memory via said multiplexer means.
Claim 19
Dependent Claim
42 words
The video random access memory recited in claim 15 wherein said improvement further comprises mask register means loaded from said bi-directional random port, data in said mask register means masking data read into said first serial access memory via said multiplexer means.
Claim 20
Dependent Claim
45 words
The video random access memory recited in claim 14 wherein said improvement further comprises align register means connected to said first serial access memory for controlling with said serial access memory address counter means a range of addresses addressed in said first serial access memory.
References Cited (Backward Citations)
No citation records indexed.
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