EP0485086A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Dielectric layers for integrated circuits
Assignee: AT&T Inc
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Filing: 1991-10-22
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Granted: —
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Expires: 2011-10-22
Abstract
Abstract In an illustrative embodiment, the present invention includes the formation of three dielectric layers (e.g., 21,27,29), one upon another, and the planarizing or etching back of the third layer (e.g., 29). Various embodiments may feature a second sandwiched layer (e.g., 35) which tends to inhibit mobile ion transport from the layer above the second layer (e.g., 37) to the layer (e.g., 21) below the second layer (e.g., 35).
Inventors
- 👤 Hongzong Chew
- 👤 Alain Simon Harrus
- 👤 Graham William Hills
- 👤 Morgan Jones Thoma
- 👤 Chen-Hua Douglas Yu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 20:17
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10W20/01; H10W20/071; H10W20/074; H10W20/075; H10W20/092
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
76 words
A method of semiconductor integrated circuit fabrication comprising: forming a first dielectric layer (e.g., 21) upon a substrate (e.g., 11); AND CHARACTERIZED BY forming a second dielectric layer (e.g., 27) upon said first dielectric layer (e.g., 21), said second dielectric (e.g., 27) being a material capable of substantially inhibiting mobile ion transport; forming a third dielectric layer (e.g., 29) upon said second dielectric layer (e.g., 27), at least partially etching back said third layer (e.g., 29).
Claim 2
Dependent Claim
40 words
The process of claim 1 further including the step of forming said first (e.g., 21), second (e.g., 27) and third (e.g., 29) layers with thicknesses sufficient to prevent substantial image charge inducement in said substrate to adversely affect circuit performance.
Claim 3
Dependent Claim
29 words
The process of claim 1 in which said first dielectric layer (e.g., 21) is formed from precursors chosen from the group consisting of silane, TEOS, TMOS, DADBS, and TMCTS.
Claim 4
Dependent Claim
24 words
The process of claim 1 in which said substrate (e.g., 11) is a material chosen from the group consisting of silicon and silicon dioxide.
Claim 5
Dependent Claim
28 words
The process of claim 1 in which said second dielectric layer (e.g., 27) is chosen from the group consisting of silicon nitride, and silicon dioxide doped with phosphorous.
Claim 6
Dependent Claim
29 words
The process of claim 1 in which said third dielectric layer (e.g., 29) is formed from precursors chosen from the group consisting of silane, TEOS, TMOS, DADBS, and TMCTS.
Claim 7
Dependent Claim
17 words
The process of claim 1 in which said etching back step is accomplished by reactive ion etching.
Claim 8
Dependent Claim
31 words
The process of claim 1 in which said etching back step is accomplished by depositing and leveling a resist material and then etching both said resist and said third dielectric layer.
Claim 9
Dependent Claim
51 words
The process of claim 1 in which a fourth layer (e.g., 35) is formed upon said second layer (e.g., 33), before formation of said third layer (e.g., 37), and said fourth layer (e.g., 35) is a dielectric chosen from the group consisting of silicon nitride and silicon dioxide doped with phosphorous.
Claim 10
Dependent Claim
97 words
The method of claim 1 in which said first layer (e.g., 21) is made from TEOS and covers at least one conductive runner (e.g., 13) and has a thickness of 0.8µm±0.1µm; said second layer (e.g., 27) is made from silicon nitride and has a thickness of 0.2µm±0.05µm; said third layer (e.g., 29) is made from TEOS and has an initial thickness of 1.5µm±0.5µm; said third layer (e.g., 29) is partially etched back, leaving at least a thickness of 0.1µm above said runner (e.g., 13); and at least one second conductive runner is formed upon said third layer.
References Cited (Backward Citations)
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