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I.C. card

Assignee: Mitsubishi Electric Corp
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Filing: 1991-10-02
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Granted: —
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Expires: 2011-10-02
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Abstract

Abstract An IC card comprises a first semiconductor memory such as a 256 K bits RAM (1) for storing main data, a second semiconductor memory such as 64 K bits EEPROM (2) for storing physical information concerning the IC card, e.g., size, capacity and access time, a control circuit (3) for selectively enabling one of the first and second semiconductor memories to operate, an address BUS (5) connected to the first and second semiconductor memories, a data BUS (7) connected to the first and second semiconductor memories, and a decoder (4) for decoding a write control signal (WE) for the second semiconductor memory using part of the address signal necessary for making access to the second semiconductor memory and delivering the decoded write control signal to the second semiconductor memory. Consequently, the area in the second semiconductor memory is divided into a non-rewritable region which does not permit rewrite of the data and a writable region which permits rewrite of the data.

Inventors

  • 👤 Sanemitsu c/o Mitsubishi Denki K.K. Yoshikado

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-04 20:49
CPC Classifications
G; G07; G07F; G07F7/00; G07F7/08; G07F7/10; G07F7/1008; G06; G06Q; G06Q20/00; G06Q20/30; G06Q20/34; G06Q20/341; G06Q20/357; G07F7/0806; G07F7/0813; G07F7/082

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 103 words
An IC card comprising: a first semiconductor memory for storing main data; a second semiconductor memory for storing physical information concerning the IC card; a control circuit for selectively enabling one of said first and second semiconductor memories to operate; an address BUS connected to said first and second semiconductor memories; a data BUS connected to said first and second semiconductor memories; and a decoder for decoding a write control signal for said second semiconductor memory using part of the address signal necessary for making access to said second semiconductor memory and delivering the decoded write control signal to said second semiconductor memory.
Claim 2
Dependent Claim 66 words
An IC card according to Claim 1, wherein said address BUS has a plurality of signal lines corresponding to a plurality of bits, said decoder selectively decoding said write control signal for said second semiconductor memory in accordance with the levels of at least one of said plurality of signal lines, whereby said second semiconductor memory has a rewritable memory region and a non-rewritable memory region.
Claim 3
Dependent Claim 20 words
An IC card according to Claim 2, wherein said non-rewritable memory region stores said physical information concerning the IC card.
Claim 4
Dependent Claim 15 words
An IC card according to Claim 1, wherein said second semiconductor memory has a PROM.
Claim 5
Dependent Claim 16 words
An IC card substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

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