Patent EP0482868A2 successfully refreshed from Google Patents.
EP0482868A2
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An address buffer circuit with transition-based latching
Assignee: STMicroelectronics lnc USA
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Filing: 1991-10-21
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Granted: —
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Expires: 2011-10-21
Abstract
Abstract An input buffer circuit having a latching function controlled by a transition detection circuit is disclosed. The input stage of the input buffer is connected to a delay stage, and to a transition detection circuit. The output of the delay stage is connected to a pass gate, which is controlled by the output of the transition detection circuit; a latch is connected to the other side of the pass gate. The transition detection circuit produces a pulse responsive to a transition, and the pass gate is turned off during the length of the pulse, with the latch maintaining and presenting the state of the input prior to the transition. After the pulse is complete, the new value of the input signal is latched and presented to the circuit. Since the pass gate is turned off during the transition detection pulse, a short and spurious transition at the input terminal is isolated from the latch by the pass gate (with the transition detection pulse lengthened), and does not appear at the output of the input buffer circuit.
Inventors
- 👤 David Charles Mcclure
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 09:51
CPC Classifications
H; H03; H03K; H03K19/00; G; G11; G11C; G11C8/00; G11C8/18; G11C8/06
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
108 words
An input buffer circuit, comprising: a transition detection circuit having an input coupled to an input terminal, and having an output for presenting a pulse responsive to detection of a transition at the output of said input terminal; a latch, having an input and an output, the output of said latch coupled to the output of said input buffer circuit; and a pass gate coupled between said input terminal and the input of said latch, said pass gate controlled by the output of said transition detection circuit so that the pass gate is non-conductive during such time as the output of said transition detection circuit presents said pulse.
Claim 2
Dependent Claim
15 words
The input buffer circuit of claim 1, wherein said input terminal is an address terminal.
Claim 3
Dependent Claim
21 words
The input buffer circuit of claim 1, further comprising: a delay gate coupled between said input terminal and said pass gate.
Claim 4
Dependent Claim
124 words
The input buffer circuit of claim 1, wherein said transition detection circuit comprises: a first leg, comprising: a logic function having a first input coupled to said input terminal; and a delay gate, coupled between said input terminal and a second input of said logic function; a second leg, comprising: a logic function having a first input coupled to said input terminal; and a delay gate, coupled between said input terminal and a second input of said logic function; wherein said input terminal is coupled to said first and second legs in a complementary manner; and an output logic function, having inputs coupled to the outputs of said logic functions in said first and second legs, and having an output for presenting said pulse.
Claim 5
Dependent Claim
20 words
The input buffer of claim 4, further comprising: a delay stage coupled between said input terminal and said pass gate.
Claim 6
Dependent Claim
27 words
The input buffer of claim 5, wherein the delay of said delay stage is less than the delay in said delay gates of said transition detection circuit.
Claim 7
Dependent Claim
40 words
The input buffer of claim 5, wherein the delay of said delay stage is of such a value that a transition at said input terminal reaches said pass gate after said transition detection circuit presents said pulse at its output.
Claim 8
Independent Claim
96 words
A method for controlling the buffering of an input signal at a terminal of an integrated circuit, comprising: detecting transitions of said input signal; generating a pulse responsive to detection of a transition of said input signal, said pulse having a first edge, and a second edge delayed from said first edge; after said first edge of said pulse, isolating said terminal from a latch, said latch having an output coupled to a node of said integrated circuit; and after said second edge of said pulse, latching the state of said input signal in said latch.
Claim 9
Dependent Claim
21 words
The method of claim 8, wherein a transition of said input signal corresponds to a new operating cycle of said circuit.
Claim 10
Dependent Claim
28 words
The method of claim 9, wherein, prior to said first edge of said pulse, said latch stores the state of said input signal from the prior operating cycle.
Claim 11
Dependent Claim
48 words
The method of claim 8, wherein said isolating step is performed by controlling a pass gate coupled between said input terminal and said latch; and further comprising: delaying said input signal; and applying said delayed input signal to said pass gate after said first edge of said pulse.
Claim 12
Dependent Claim
17 words
The method of claim 8, further comprising: applying said pulse to other portions of said integrated circuit.
Claim 13
Dependent Claim
14 words
The method of claim 8, wherein said integrated circuit is a static read/write memory.
Claim 14
Dependent Claim
41 words
The method of claim 8, wherein said generating step comprises: generating said first edge of said pulse responsive to detecting said transition; and generating said second edge of said pulse responsive to a selected delay time expiring after detecting said transition.
Claim 15
Dependent Claim
55 words
The method of claim 14, further comprising: after said step of generating said first edge of said pulse, detecting an additional transition of said input signal prior to said selected delay time expiring; and responsive to detecting said additional transition, delaying said second edge of said pulse for a selected delay after said additional transition.
Claim 16
Dependent Claim
48 words
The method of claim 15, wherein said isolating step is performed by controlling a pass gate coupled between said input terminal and said latch; and further comprising: delaying said input signal; and applying said delayed input signal to said pass gate after said first edge of said pulse.
Claim 17
Dependent Claim
27 words
The method of claim 16, wherein the delaying of said input signal is for a time shorter than the delaying of said second edge of said pulse.
Claim 18
Dependent Claim
115 words
An input buffer circuit for buffering the application of an input signal to a terminal of an integrated circuit, comprising: means for detecting a transition of said input signal, and for producing at an output a signal responsive to a transition of said input signal; a latch, having an input and an output, said output of said latch coupled to a node in said integrated circuit; and a pass gate, coupled between said terminal and the input of said latch, and having a control terminal coupled to the output of said detecting means, for isolating said terminal from the input of said latch responsive to said detecting means detecting a transition of said input signal.
Claim 19
Dependent Claim
57 words
The circuit of claim 18, wherein said signal produced by said detecting means comprises a pulse having a first edge and a second edge; and wherein said pass gate isolates said terminal from the input of said latch during the time after said first edge of said pulse and prior to the second edge of said pulse.
Claim 20
Dependent Claim
21 words
The circuit of claim 19, further comprising: means for delaying said input signal, coupled between said terminal and said pass gate.
Claim 21
Dependent Claim
39 words
The circuit of claim 20, wherein said detecting means further is for delaying said second edge responsive to detecting a second transition of sail input signal occurring prior to said detecting means producing said second edge of said pulse.
References Cited (Backward Citations)
No citation records indexed.
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