Semiconductor integrated circuit provided with emitter coupled logic input/output buffers

Claim 1

A semiconductor integrated circuit (40, 50) comprising: a plurality of first Emitter Coupled Logic (ECL) input buffers (21₁-21 n ) driven by a specific number of plural first power supplies, and for inputting a signal of the ECL level from the external; a plurality of first ECL output buffers (22₁-22 n )driven by said specific number of second power supplies, and for outputting a signal of said ECL level to the external; a plurality of second test ECL input buffers (23₁-23 n ) driven by said specific number of first power supplies, and for inputting a test signal of said ECL level from the external when the said semiconductor integrated circuit is assembled, a plurality of second test ECL output buffers (24₁-24 n ) driven by said specific number of second power supplies, and for outputting a test signal of said ECL level to the external when said semiconductor integrated circuit (40, 50) is assembled; said specific number of first drive voltage supply lines (41a, 41b, 34b) for connecting said first power supplies and said first input buffers in order to deliver voltages for driving said first input buffers in an ordinary use state after said semiconductor integrated circuit (40, 50) is assembled; said specific number of second drive voltage supply lines (42a, 42b, 34b) for connecting said second power supplies and said first output buffers in order to deliver voltages for driving said first output buffers in an ordinary use state after said semiconductor integrated circuit (40, 50) is assembled; third drive voltage supply lines (43a, 43b, 34b) adapted so that normal power supply voltages are delivered to said second input buffers by said specific number of third power supplies only when said semiconductor integrated circuit is assembled, and that no drive voltage is delivered in an ordinary use state after said semiconductor integrated circuit (40, 50) is assembled; and fourth drive voltage supply lines (44a, 44b, 34b) adapted so that normal power supply voltages are delivered to said second output buffers by said specific number of fourth power supplies only when said semiconductor integrated circuit (40, 50) is assembled, and that no drive voltage is delivered in an ordinary use state after said semiconductor integrated circuit (40, 50) is assembled.