EP0482658A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit provided with emitter coupled logic input/output buffers
Assignee: Toshiba Corp
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Filing: 1991-10-25
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Granted: —
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Expires: 2011-10-25
Abstract
Abstract A semiconductor circuit (40) comprises a plurality of first Emitter Coupled Logic (ECL) input buffer (21₁...21 n ) and output buffers (22₁...22 n ), which are driven by a specific number (m ≧ 2) power supplies. Further it comprises a plurality of ECL test input buffers (23₁...23 n ) and test output buffers (24₁...24 n ) driven by a specific number of power supplies (m ≧ 2). The power supply lines (41a,41b,42a,42b) to the ECL input and output buffers are independent of the power supply lines of the test input and output buffers. Power is supplied to the test input and output buffers only during assembly of the integrated circut.
Inventors
- 👤 Kenji Sakaue
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 18:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812; H03K19/0008
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
372 words
A semiconductor integrated circuit (40, 50) comprising: a plurality of first Emitter Coupled Logic (ECL) input buffers (21₁-21 n ) driven by a specific number of plural first power supplies, and for inputting a signal of the ECL level from the external; a plurality of first ECL output buffers (22₁-22 n )driven by said specific number of second power supplies, and for outputting a signal of said ECL level to the external; a plurality of second test ECL input buffers (23₁-23 n ) driven by said specific number of first power supplies, and for inputting a test signal of said ECL level from the external when the said semiconductor integrated circuit is assembled, a plurality of second test ECL output buffers (24₁-24 n ) driven by said specific number of second power supplies, and for outputting a test signal of said ECL level to the external when said semiconductor integrated circuit (40, 50) is assembled; said specific number of first drive voltage supply lines (41a, 41b, 34b) for connecting said first power supplies and said first input buffers in order to deliver voltages for driving said first input buffers in an ordinary use state after said semiconductor integrated circuit (40, 50) is assembled; said specific number of second drive voltage supply lines (42a, 42b, 34b) for connecting said second power supplies and said first output buffers in order to deliver voltages for driving said first output buffers in an ordinary use state after said semiconductor integrated circuit (40, 50) is assembled; third drive voltage supply lines (43a, 43b, 34b) adapted so that normal power supply voltages are delivered to said second input buffers by said specific number of third power supplies only when said semiconductor integrated circuit is assembled, and that no drive voltage is delivered in an ordinary use state after said semiconductor integrated circuit (40, 50) is assembled; and fourth drive voltage supply lines (44a, 44b, 34b) adapted so that normal power supply voltages are delivered to said second output buffers by said specific number of fourth power supplies only when said semiconductor integrated circuit (40, 50) is assembled, and that no drive voltage is delivered in an ordinary use state after said semiconductor integrated circuit (40, 50) is assembled.
Claim 2
Dependent Claim
70 words
A semiconductor integrated circuit (40, 50) as set forth in claim 1, wherein there is employed an arrangement such that the number of said third drive voltage supply lines (43a) is the same as said specific number of said third power supplies, and that one of said specific number of third supply lines (34b) is common to a corresponding one of said specific number of first drive voltage supply lines.
Claim 3
Dependent Claim
70 words
A semiconductor integrated circuit (40, 50) as set forth in claim 1, wherein there is employed an arrangement such that the number of said fourth drive voltage supply lines (44a) is the same as said specific number of said fourth power supplies, and that one of said specific number of fourth supply lines (34b) is common to a corresponding one of said specific number of second drive voltage supply lines.
Claim 4
Dependent Claim
37 words
A semiconductor integrated circuit as set forth in claim 1, wherein said third drive voltage supply lines (43a, 43b) are separately formed on a Large Scale Integrated circuit (LSI) independently of said first drive voltage supply lines.
Claim 5
Dependent Claim
37 words
A semiconductor integrated circuit as set forth in claim 1, wherein said fourth drive voltage supply lines (44a, 44b) are separately formed on a Large Scale Integrated circuit (LSI) independently of said second drive voltage supply lines.
Claim 6
Dependent Claim
68 words
A semiconductor integrated circuit (40, 50) as set forth in claim 1, wherein said plurality of first power supplies for driving said first and second input buffers (21₁-21 n , 23₁-23 n ) are comprised of two power supplies, and wherein said plurality of second power supplies for driving said first and second output buffers (22₁-22 n , 24₁-24 n ) are also comprised of two power supplies.
Claim 7
Dependent Claim
56 words
A semiconductor integrated circuit (40, 50) as set forth in claim 1, wherein said first and second input buffers (21₁-21 n , 23₁-23 n ) and said first and second output buffers (22₁-22 n , 24₁-24 n )are comprised of n (n is equal to 2 or more) number of input and output buffer circuits, respectively.
Claim 8
Dependent Claim
69 words
A semiconductor integrated circuit (40, 50) as set forth in claim 7, wherein one of said input buffer circuits performs logical operation of a signal of said ECL level inputted thereto thus to output a signal of the CMOS level, and wherein one of said output buffer circuits performs logical operation of a signal of said CMOS level inputted thereto thus to output a signal of the ECL level.
References Cited (Backward Citations)
No citation records indexed.
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