Patent EP0476487A2 successfully refreshed from Google Patents.
EP0476487A2
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System for reproducing timing clock signal
Assignee: Fujitsu Ltd
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Filing: 1991-09-10
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Granted: —
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Expires: 2011-09-10
Abstract
Abstract A timing clock reproducing system in a digital subscriber line communication for extracting an optimum phase of a clock signal, and comprising: a line equalizer (111) for shaping a waveform distorted by a transmission through a cable line; a PLL circuit (112) for generating a sampling timing control signal; an analog-to-digital converter (113) for sampling a signal received from the line equalizer at a timing controlled by the sampling timing control, and for converting the received signal into a digital signal; a decision feedback equalizer (114), for outputting tap coefficients including a precursor equalizing tap coefficient; and an evaluating function deriving means (115) for deriving an evaluating function the based the PLL circuit (112) being controlled by the valuating function for adjusting a sampling timing of the analog-to-digital converter. <IMAGE>
Inventors
- 👤 Seiji Fujitsu Ibukino Shataku A202 Miyoshi
- 👤 Takashi Sato
- 👤 Kenji Pakuhaitsu Yurigaoka 106 Takato
- 👤 Hiroyuki Ujiie
- 👤 Yozo Dai-3 Ebisuso 102 Iketani
- 👤 Kinji Kawada
- 👤 Misao Fukuda
- 👤 Hiroaki Itokawa
- 👤 Norio Ueno
- 👤 Yutaka Awata
- 👤 Kouji Tokiwa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 17:34
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/0058; H04L25/00; H04L25/02; H04L25/03; H04L25/03878; H04L25/03885; H04L5/00; H04L5/14; H04L5/1469; H04L25/03006; H04L2025/03433; H04L2025/03439; H04L2025/03445; H04L2025/03471; H04L2025/03484; H04L2025/0349; H04L2025/03503; H04L2025/03592; H04L2025/03598; H04L2025/03681; H04L2025/037
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
153 words
A timing clock reproducing system in a digital subscriber line communication for extracting an optimum phase of a clock signal, comprising: a line equalizer (111) for shaping a waveform distorted by a transmission through cable line; a PLL circuit (12) for generating a sampling timing control signal; an analog-to-digital converter (13) for sampling a signal received from said line equalizer at a timing controlled by said sampling timing control signal from said PLL circuit, and for converting said received signal into a digital signal; a decision feedback equalizer (114) , connected to the output of said analog-to-digital converter, for outputting tap coefficients including a precursor equalizing coefficient; and an evaluating function deriving means (115), connected to the output of said decision feedback equalizer, for deriving an evaluating function based said precursor equalizing tap coefficientr; said PLL circuit (112) being controlled by said evaluating function for adjusting a sampling timimg of said analog-to-digital converter.
Claim 2
Dependent Claim
40 words
A timing clock reproducing system as set forth in claim 1, wherein said decision feedback equalizer includes means (18) for periodically updating tap coefficients including said precursor equalizing tap coefficient on the basis of symbol values of the receiving signals.
Claim 3
Dependent Claim
47 words
A timing clock reproducing system as set forth in claim 2, wherein said decision feedback equalizer includes means for calculating a symbol value of the currently received signal on the basis of an input derived from a received signal sample value sampled at the current sampling timing.
Claim 4
Dependent Claim
38 words
A timing clock reproducing system as set forth in claim 3, wherein said decision feedback equalizer further comprises means for deriving a residual error on the basis of said input and output of said symbol value calculating means.
Claim 5
Dependent Claim
41 words
A timing clock reproducing system as set forth in claim 4, wherein said decision feedback equalizer further comprises means for deriving an intermediate value for use in said means for updating said tap coefficient on the basis of said residual error.
Claim 6
Dependent Claim
35 words
A timing clock reproducing system as set forth in claim 5, wherein said tap coefficient updating means periodically updates said tap coefficient within one sampling cycle thereby obtain a predetermined convergence of said residual error.
Claim 7
Dependent Claim
61 words
A timing clock reproducing system as set forth in claim 6, wherein said tap coefficient updating means compares the residual error value derived with respect to the instantaneous value of a tap coefficient with a predetermined threshold value to thereby repeat an updating operation for said tap coefficient as long as said residual error is greater than said predetermined threshold value.
Claim 8
Dependent Claim
40 words
A timing clock reproducing system as set forth in claim 1, wherein said evaluating function deriving means controls said PLL circuit for adjusting a sampling timing of said received signal, to reduce the evaluating function for a precursor type equalizer.
Claim 9
Dependent Claim
43 words
A timing clock reproducing system as set forth in claim 1, wherein said evaluating function deriving means controls said PLL circuit for adjusting a sampling timing of said received signal to increase the evaluating function by one for a peak detection type equalizer.
Claim 10
Dependent Claim
53 words
A timing clock reproducing system as set forth in claim 1, wherein said evaluating function deriving means (115) receives said precursor equalizing tap coefficient C₋₁ and a main cursor equalizing tap coefficient C₀ for deriving said evaluating function for controlling said PLL circuit (112) and adjusting a sampling timing of said analog-to-digital converter.
Claim 11
Dependent Claim
40 words
A timing clock reproducing system as set forth in claim 10, wherein said evaluating function deriving means controls said PLL circuit for adjusting a sampling timing of said received signal to reduce the evaluating function for a precursor type equalizer.
Claim 12
Dependent Claim
43 words
A timing clock reproducing system as set forth in claim 10, wherein said evaluating function deriving means controls said PLL circuit for adjusting a sampling timing of said received signal to increase the evaluating function by one for a peak detection type equalizer.
Claim 13
Dependent Claim
53 words
A timing clock reproducing system as set forth in claim 7 or 10, which further comprises an automatic gain control circuit for automatically controlling a level of said received signal, and the gain of said automatic gain control circuit is controlled on the basis of the output of said evaluating function deriving means.
Claim 14
Dependent Claim
296 words
A timing clock reproducing system as set forth in claim 1, wherein said decision feedback equalizer assumes that the current symbol value of periodically transmitted codes is a n , the symbol values of one to N preceding cycles are respectively a (n-1) to a n-N , the symbol value of the next cycle is a₋₁, the impulse response sequence corresponding thereto is respectively h₀, h₁ to h N , and the impulse response of the precursor is h₋₁, and a receiving signal sample value X n can be expressed by the following equation due to presence of an intersymbol interference: X n =h₋₁a₋₁-h₀a n +h₁a n-1 +....+h N a n-N wherein the decision feedback equalizer comprises: a tap coefficient updating means (10) for deriving equalizing tap coefficients C₁ to C N respectively corresponding to said impulse response sequence h₁ to h N and precursor equalizing tap coefficient C₋₁ and outputting respectively C₁a n-1 + C₂a n-2 + ... + C N a n-N , based on a residual error predicting intermediate value in a preceding sampling cycle corresponding to a difference between an output and an input of a received symbol determining unit which determines a symbol value of a received signal, a value derived by subtracting a product of said precursor equalizing tap coefficient C₋₁ and a current output of said received symbol determining unit, from said residual error predicting intermediate value, said current receiving symbol value a n , and said a n-1 to a n-N ; a subtracting means (11) for deriving a difference between said receiving sample value and the output of said tap coefficient updating means; said received symbol determining means (12) receiving an output of said subtracting means (11) and outputting the symbol value of the current received symbol.
Claim 15
Dependent Claim
245 words
A timing clock generating system as set forth in claim 1, wherein said decision feedback equalizer comprises a symbol coder for use in a line equalizer incorporated in a data transceiver for communication through a digital customer line using 2B1Q code for compensating a transmission loss through said customer cable line, said symbol coder comprising: means (301) for defining a first pair of threshold levels (±A) having an absolute value which is greater than 0 and smaller than 1 and a second pair of threshold levels (±B) having an absolute value which is greater than 1 and smaller than 3; means (302) for detecting an input signal level between said first pair of threshold levels for setting a received symbol value of said input signal to 0; means (303) responsive to an input signal having a level greater than a positive value (+A) of said first pair of threshold levels and setting the received symbol value to +1 when said input signal level is smaller than a positive value (+B) of said second pair of threshold levels, and otherwise setting said received symbol value to +3; and means (304) responsive to input signal having a level smaller than a negative value (-A) of said first pair of threshold level, and setting the received symbol value to -1 when said input signal level is greater than a negative value (-B) of said second pair of threshold levels and otherwise, setting said received symbol value to -3.
Claim 16
Dependent Claim
22 words
A timing clock reproducing system as set forth in claim 15, wherein said symbol coder is applied to a 2B1Q code system.
Claim 17
Dependent Claim
300 words
A decision feedback type line equalizer for removing an intersymbol interference between codes, wherein the current symbol value of periodically transmitted codes is assumed as a n , the symbol values of one to N preceding cycles are respectively assumed as a (n-1) to a n-N , the symbol value of the next cycle is a₋₁, the impulse response sequence corresponding thereto are respectively assumed as h₀, h₁ to h N , and the impulse response of the precursor is assumed as h₋₁, and a received signal sample value X n can be expressed by the following equation, due to presence of intersymbol interferencey: X n =h₋₁a₋₁-h₀a n +h₁a n-1 +....+h N a n-N wherein the decision feedback equalizer comprises: a tap coefficient updating means (10) for deriving equalizing tap coefficients C₁ to C N respectively corresponding to said impulse response sequence h₁ to h N and precursor equalizing tap coefficient C₋₁ and outputting respective of C₁a n-1 + C₂a n-2 + ... + C N a n-N , based on a residual error predicting intermediate value in a preceding sampling cycle corresponding to a difference between an output and an input of a received symbol determining unit which determining a symbol value of a received signal, a value derived by subtracting a product of said precursor equalizing tap coefficient C₋₁ and a current output of said received symbol determining unit, from said residual error predicting intermediate value, said current received symbol value a n , and said a n-1 to a n-N ; a subtracting means (11) for deriving a difference between said received sample value and the output of said tap coefficient updating means; said received symbol determining means (12) receiving an output of said subtracting means (11) and outputting the symbol value of the current received symbol.
Claim 18
Dependent Claim
20 words
A timing clock reproducing system as set forth in claim 1, wherein the system is incorporated in a data transceiver.
Claim 19
Dependent Claim
227 words
A symbol coder for use in a line equalizer incorporated in a data transceiver for communication through a digital customer line using a 2B1Q code for compensating a transmission loss through said customer cable line, comprising: means (301) for defining a first pair of threshold levels (±A) having an absolute value which is greater than 0 and smaller than 1 and a second pair of threshold levels (±B) having an absolute value which is greater than 1 and smaller than 3; means (302) for detecting an input signal level between said first pair of threshold levels for setting a received symbol value of said input signal to 0; means (303) responsive to an input signal having a level greater than a positive value (+A) of said first pair of threshold levels and setting the received symbol value to +1 when said input signal level is smaller than a positive value (+B) of said second pair of threshold levels, and otherwise, setting said received symbol value to +3; and means (304) responsive to an input signal having a level smaller than a negative value (-A) of said first pair of threshold levels and setting the received symbol value to -1 when said input signal level is greater than a negative value (-B) of said second pair of threshold levels, and otherwise, setting said received symbol value to -3.
References Cited (Backward Citations)
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