Patent US1728646A successfully refreshed from Google Patents.
Patent EP0475468A2 successfully refreshed from Google Patents.
EP0475468A2
Expired / Lapsed
EP
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Phase comparator for a digital phase locked loop
Assignee: Motorola Solutions Inc
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Filing: 1984-12-31
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Granted: —
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Expires: 2004-12-31
Abstract
Abstract An improved multiple frequency digital phase-locked loop circuit 10 is described. The improved digital phase-locked loops utilizes a single circuit 12 to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal 30 with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The multiple frequency provides frequency adjustments by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controllable clock signal. The improved multifrequency digital phase-locked loop is suitable for use as a tone detector with the addition of a lock detector 22 wherein the phase-locked loop can be programmed for a plurality of known operating frequencies.
Inventors
- 👤 Steven N. Levine
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 07:06
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/003; H03D13/004; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992; H03L7/0993; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
461 words
A phase comparator for providing output signals indicating the relative phase of first and second input signals comprising: a) means for inputting a first input signal and an inverted first input signal; b) means for generating a first derived signal from said first input signal at twice the frequency of said first input signal; c) means for inputting a second input signal; d) first flip-flop means having delay and clock inputs and inverted and non-inverted outputs, said delay input coupled to said first input signal and said clock input coupled to said first derived signal; e) second flip-flop means having delay and clock inputs and inverted and non-inverted outputs, said delay input coupled to said first input signal and said clock input coupled to said first derived signal; f) third flip-flop means having delay and clock inputs and inverted and non-inverted outputs, said delay input coupled to said second input signal and said clock input coupled to said inverted first input signal; g) fourth flip-flop means having delay, clock and reset inputs and a non-inverted output, said delay input coupled to the non-inverted output of said first flip-flop means and said clock input coupled to the non-inverted output of said second flip-flop means; h) fifth flip-flop means having delay, clock and reset inputs and a non-inverted output, said delay input coupled to the inverted output of said first flip-flop means and said clock input coupled to the non-inverted output of said second flip-flop means; (i) sixth flip-flop means having a delay, clock and reset inputs and a non-inverted output, said delay input coupled to the non-inverted output of said third flip-flop means and said clock input coupled to the inverted output of said second flip-flop means; j) seventh flip-flop means having delay, clock and reset inputs and a non-inverted output, said delay input coupled to the inverted output of said third flip-flop means and said clock input coupled to the inverted output of said second flip-flop means; k) first OR gate means having first and second inputs and an output, said first input coupled to the non-inverted output of said fourth flip-flop means, said second input coupled to the non-inverted output of said seventh flip-flop means and said output indicating that the phase of the first input signal lags the phase of the second input signal; I) second OR gate means having first and second inputs and an output, said first input coupled to the non-inverted output of said sixth flip-flop means and said output indicating that the phase of the first input signal leads the phase of the second input signal; and m) reset means coupled to the reset inputs of said fourth, fifth, sixth and seventh flip-flop means for resetting said flip-flops after a phase comparison has been completed.
Claim 2
Dependent Claim
461 words
A phase comparator for providing output signals indicating the relative phase of first and second input signals comprising: a) means for inputting a first input signal and an inverted first input signal; b) means for generating a first derived signal from said first input signal at twice the frequency of said first input signal; c) means for inputting a second input signal; d) first flip-flop means having delay and clock inputs and inverted and non-inverted outputs, said delay input coupled to said first input signal and said clock input coupled to said first derived signal; e) second flip-flop means having delay and clock inputs and inverted and non-inverted outputs, said delay input coupled to said first input signal and said clock input coupled to said first derived signal; f) third flip-flop means having delay and clock inputs and inverted and non-inverted outputs, said delay input coupled to said second input signal and said clock input coupled to said inverted first input signal; g) fourth flip-flop means having delay, clock and reset inputs and a non-inverted output, said delay input coupled to the non-inverted output of said first flip-flop means and said clock input coupled to the non-inverted output of said second flip-flop means; h) fifth flip-flop means having delay, clock and reset inputs and a non-inverted output, said delay input coupled to the inverted output of said first flip-flop means and said clock input coupled to the non-inverted output of said second flip-flop means; (i) sixth flip-flop means having a delay, clock and reset inputs and a non-inverted output, said delay input coupled to the non-inverted output of said third flip-flop means and said clock input coupled to the inverted output of said second flip-flop means; j) seventh flip-flop means having delay, clock and reset inputs and a non-inverted output, said delay input coupled to the inverted output of said third flip-flop means and said clock input coupled to the inverted output of said second flip-flop means; k) first OR gate means having first and second inputs and an output, said first input coupled to the non-inverted output of said fourth flip-flop means, said second input coupled to the non-inverted output of said seventh flip-flop means and said output indicating that the phase of the first input signal lags the phase of the second input signal; I) second OR gate means having first and second inputs and an output, said first input coupled to the non-inverted output of said sixth flip-flop means and said output indicating that the phase of the first input signal leads the phase of the second input signal; and m) reset means coupled to the reset inputs of said fourth, fifth, sixth and seventh flip-flop means for resetting said flip-flops after a phase comparison has been completed.
Claim 3
Dependent Claim
160 words
A phase comparator for use with a digital phase-locked loop or similar phase sensitive device, providing output signals indicating the relative phase of first and second input signals and having inputs for receiving a first derived signal that has twice the frequency of said first input signal and for receiving an external signal for resetting or temporarily disabling the phase comparator said phase comparator comprising; a) first latch means, clocked by said first derived clock signal, for sampling the first input signal and providing an output; b) second latch means, clock by said first input signal, for sampling the second input signal and providing outputs indicating the relative phase relationship between said first and second input signals; c) storing means, coupled to outputs of said second latch means and clocked by the output of said first latch means, for storing the outputs of said second latch means; and d) means, responsive to said external signal, for resetting said storing means.
Claim 4
Dependent Claim
160 words
A phase comparator for use with a digital phase-locked loop or similar phase sensitive device, providing output signals indicating the relative phase of first and second input signals and having inputs for receiving a first derived signal that has twice the frequency of said first input signal and for receiving an external signal for resetting or temporarily disabling the phase comparator said phase comparator comprising; a) first latch means, clocked by said first derived clock signal, for sampling the first input signal and providing an output; b) second latch means, clock by said first input signal, for sampling the second input signal and providing outputs indicating the relative phase relationship between said first and second input signals; c) storing means, coupled to outputs of said second latch means and clocked by the output of said first latch means, for storing the outputs of said second latch means; and d) means, responsive to said external signal, for resetting said storing means.
Claim 5
Dependent Claim
29 words
The apparatus of claim 2 wherein the phase comparator can be programmably altered to provide a phase comparator on both leading and lagging edges of said first input signal.
Claim 6
Independent Claim
80 words
A method for comparing the relative phase relationship between a received digital data signal and a digital reference clock and producing phase adjust control signals indicating the results of comparing, comprising the steps of; sampling the received digital data signal at the time of each predetermined transition of the digital reference clock and producing phase comparison signals; after a predetermined time delay, making available the phase comparison signals as phase adjust control signals until receipt of an external reset signal.
Claim 7
Independent Claim
80 words
A method for comparing the relative phase relationship between a received digital data signal and a digital reference clock and producing phase adjust control signals indicating the results of comparing, comprising the steps of; sampling the received digital data signal at the time of each predetermined transition of the digital reference clock and producing phase comparison signals; after a predetermined time delay, making available the phase comparison signals as phase adjust control signals until receipt of an external reset signal.
Claim 8
Independent Claim
239 words
A method for comparing the relative phase relationship between a received digital data signal and a digital reference clock and producing composite phase adjust control signals indicating the results of comparing, comprising the steps of: sampling the received digital data signal at the time of each positive transition of the digital reference clock and producing positive-edge phase comparison signals; after a predetermined time delay, making available the positive-edge phase comparison signals as positive-edge phase adjust control signals; storing the positive-edge phase adjust control signals until receipt of an external reset signal; and, unless inhibited by an external control signal, sampling the received digital data signal at the time of each negative transition of the digital reference clock and producing negative-edge phase comparison signals; after a predetermined time delay, making available the positive-edge phase comparison signals as positive-edge phase adjust control signals; storing the positive-edge phase adjust control signals until receipt of an external reset signal; and, unless inhibited by an external control signal, sampling the received digital data signal at the time of each negative transition of the digital reference clock and producing negative-edge phase comparison signals; after a predetermined time delay, making available the negative edge phase comparison signals as negative-edge phase adjust control signals; storing the negative-edge phase adjust control signals until receipt of an external reset signal; and combining the positive- and negative-edge phase adjust control signals, respectively, to produce the composite phase adjust control signals.
Claim 9
Independent Claim
239 words
A method for comparing the relative phase relationship between a received digital data signal and a digital reference clock and producing composite phase adjust control signals indicating the results of comparing, comprising the steps of: sampling the received digital data signal at the time of each positive transition of the digital reference clock and producing positive-edge phase comparison signals; after a predetermined time delay, making available the positive-edge phase comparison signals as positive-edge phase adjust control signals; storing the positive-edge phase adjust control signals until receipt of an external reset signal; and, unless inhibited by an external control signal, sampling the received digital data signal at the time of each negative transition of the digital reference clock and producing negative-edge phase comparison signals; after a predetermined time delay, making available the positive-edge phase comparison signals as positive-edge phase adjust control signals; storing the positive-edge phase adjust control signals until receipt of an external reset signal; and, unless inhibited by an external control signal, sampling the received digital data signal at the time of each negative transition of the digital reference clock and producing negative-edge phase comparison signals; after a predetermined time delay, making available the negative edge phase comparison signals as negative-edge phase adjust control signals; storing the negative-edge phase adjust control signals until receipt of an external reset signal; and combining the positive- and negative-edge phase adjust control signals, respectively, to produce the composite phase adjust control signals.
References Cited (Backward Citations)
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