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EP0475421A2
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Dual hardware channels and hardware context switching in a graphics rendering processor
Assignee: Raytheon Co
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Filing: 1991-09-13
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Granted: —
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Expires: 2011-09-13
Abstract
Abstract An improved graphics processor (10) has rapid response to higher priority tasks. It is implemented with multiple channels of FIFO input circuits and with task interrupt and context switching capability. The graphics processor (10) servicing a first channel task is interrupted when a higher priority task is available in a second channel. Context switching facilitates interrupting of the lower priority first channel task, then saving of the context of the first channel task, then performing higher priority second channel task, then restoring the interrupted first channel task, and then continuing with the processing of the restored first channel task. It is also implemented with concurrent downloading from a host computer (14) and processing by the graphics processor (10) and implemented with general purpose graphics processing capability, including multi-level nested interrupts and nested subroutines
Inventors
- 👤 John M. Peaslee
- 👤 Jeffrey C. Malacarne
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 22:31
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F3/00; G06F3/14; G06F3/1423; G09; G09G; G09G2360/00; G09G2360/04
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
86 words
A display system characterized by: - a stored program computer (14) for generating a plurality of display lists, each display list including a plurality of graphic instructions; - a plurality of FIFOs (26, FIFO1, FIFO2) coupled to the stored program computer (14) for storing the plurality of display lists; and - a graphics processor (10) coupled to the plurality of FIFOs (26, FIFO1, FIFO2) for generating graphic pixel signals in reponse to the plurality of display lists stored by the plurality of FIFOs (26, FIFO1, FIFO2).
Claim 2
Dependent Claim
63 words
The system of claim 1, characterized by the plurality of FIFOs (26, FIFO1, FIFO2) each storing a different display list and wherein the graphics processor (10) includes a context switching circuit for switching context between different display lists stored by different ones of the plurality of FIFOs (26, FIFO1, FIFO2) and generating the graphic pixel signals in response to the different display lists.
Claim 3
Dependent Claim
121 words
The system of claim 1 or 2, characterized in that the plurality of FIFOs (26, FIFO1, FIFO2) each store a different display list and that the graphics processor (10) comprises: - an interrupt input circuit for generating an interrupt signal; and - an interrupt execution circuit coupled to the interrupt input circuit and to the plurality of FIFOs (26, FIFO1, FIFO2) for interrupting the generating of graphic pixel signals in response to the interrupt signal and in response to a first display list stored by the plurality of FIFOs (26, FIFO1, FIFO2) and for generating graphic pixel signals in response to the interrupt signal and in response to a second display list stored by the plurality of FIFOs (26, FIFO1, FIFO2).
Claim 4
Dependent Claim
31 words
The system of claim 3, characterized by a context memory coupled to the interrupt input circuit for storing the context of the first display list in response to the interrupt signal.
Claim 5
Dependent Claim
34 words
The system of claim 3 or 4, characterized by a push down stack coupled to the interrupt input circuit for storing the context of the first display list in respone to the interrupt signal.
Claim 6
Independent Claim
76 words
The system of any of claims 3 - 5, characterized by: - a restore control circuit coupled to the interrupt execution circuit for generating a restore signal in response to the second display list stored by the plurality of FIFOs (26, FIFO1, FIFO2); and - a restore execution circuit coupled to the restore control circuit and to the interrupt execution circuit for restoring the context of the first display list in response to the restore signal.
Claim 7
Independent Claim
72 words
The system of any of claims 1 - 6, characterized in that the stored program computer (14) is provided with a plurality of stored program computers each for generating at least one of the plurality of display lists and wherein the plurality of FIFOs (26, FIFO1, FIFO2) are coupled to the plurality of stored program computers (14) for storing the plurality of display lists from the plurality of stored program computers (14).
Claim 8
Independent Claim
60 words
The system of any of claims 1 - 7, characterized in that the graphics processor (10) is provided with a concurrent processing circuit (17) coupled to the plurality of FIFOs (26, FIFO1, FIFO2) for processing at least one of the plurality of display lists concurrent with the generating of the display list being generated by the stored program computer (14).
Claim 9
Independent Claim
38 words
The system of any of claims 1 - 8, characterized in that the graphics processor (10) is provided with a multi-level nested interrupt circuit for controlling the generating of the graphic pixel signals under multilevel nested interrupt control.
Claim 10
Independent Claim
35 words
The system of any of claims 1 - 9, characterized in that the graphics processor (10) is provided with a nested subroutine circuit controlling the generating of the graphic pixel signals under nested subroutine control.
Claim 11
Independent Claim
60 words
The system of any of claims 1 - 10, characterized by: - a bit map memory (22) coupled to the graphics processor (16) for storing the graphic pixel signals; and - a display monitor (24) coupled to the bit map memory (22) for generating a display in response to the graphic pixel signals stored by the bit map memory (22).
Claim 12
Independent Claim
138 words
The system of any of claims 1 - 11, characterized by: - a first and a second hardware channel comprising high and low priority processing channels; - a dual channel FIFO controller (38, 40) coupled to the first and second hardware channels that interface with a plurality of host computers (14); - said controller (38, 40) comprising means for allowing the plurality of host computers (14) to utilize the first and the second hardware channels by providing hardware context switching such that a first host computer (14) interrupts the second host computer (14) operating on the first channel by saving the second host computer's current context on an attribute stack, and upon the first host computer (14) completing an operation, the context of the first host computer (14) is restored and the second host computer (14) resumes processing.
Claim 13
Dependent Claim
213 words
A display system, characterized by: - a stored program computer (14) for generating display lists; - a display memory (26) coupled to the stored program computer (14) for storing the display lists; - a graphics processor (10) coupled to the display memory (26) for generating pixel signals in response to the display lists; - a context switching arrangement that interfaces between the stored program computer (14) and the graphics processor (10), said context switching arrangement having: - first and second hardware channels comprising high and low priority processing channels; - a dual channel FIFO controller (38, 40) coupled to the first and second hardware channels for interfacing between the stored program computer (14) and the display memory (26) and selectively loading the display lists into first and second FIFO buffers in the display memory (26); - an interrupt circuit coupled to the graphics processor (10) and the display memory (26) for interrupting the processing of a low priority display list and initiating the processing of a higher priority display list; and - a plurality of context registers (42) for storing context attributes associated with each of the display lists and a readback multiplexer (44) for restoring the attributes of the low priority display list once the higher priority display list has been processed.
Claim 14
Dependent Claim
92 words
The system of claim 13, characterized in that the dual channel FIFO controller (38, 40) comprises: - first and second hardware channels comprising high and low priority processing channels; - a dual channel FIFO controller (38, 40) coupled to the first and second hardware channels that interface with a plurality of host computers (14); - a dual channel interrupt controller that processes first and second interrupt signals; and - a programmable priority structure that defines task priority as either Int1 (high) Int2, FIFO1, FIFO2 (low) or Int1 (high), FIFO1, Int2, FIFO2 (low).
Claim 15
Dependent Claim
92 words
The system of claim 13 or 14, characterized in that said interrupt circuit is provided with means for allowing the plurality of stored program computers (14) to utilize the first and the second hardware channels by providing hardware context switching such that a first computer (14) interrupts the second computer (14) operating on the first channel by saving the second computer's current context on an attribute stack, and upon the first computer (14) completing an operation, the context of the first computer (14) is restored whereupon the second computer (14) resumes processing.
Claim 16
Independent Claim
133 words
A method of operating a display system comprising a FIFO (26, FIFO1, FIFO2) and a graphics processor (10), characterized by the steps of: - transferring a first display list to the FIFO (26, FIFO1, FIFO2); - initiating processing of the first display list by the graphics processor (10); - transferring a second display list to the FIFO (26, FIFO1, FIFO2); - interrupting processing of the first display list by the graphics processor (10) and storing a context of the first display list; - initiating processing of the second display list by the graphics processor (10); - detecting completion of processing of the second display list by the graphics processor (10); - restoring the context of the first display list; and - continuing processing of the first display list by the graphics processor (10).
Claim 17
Independent Claim
255 words
A method of operating a display system comprising a stored program computer (14) for generating display lists, each display list including a plurality of intructions, a plurality of FIFOs (26, FIFO1, FIFO2) coupled to the stored program computer (14) for storing the display lists, a graphics processor (10) coupled to the plurality of FIFOs (26, FIFO1, FIFO2) for generating pixel signals in response to a display list, an interrupt circuit coupled to the graphics processor (10) for interrupting operation thereof, and a context memory coupled to the graphics processor (10) and to the interrupt circuit for storing a context in response to interruption of operation, characterized by the steps of: - transferring a first display list from the stored program computer (14) to a first one of the plurality of the FIFOs (26, FIFO1, FIFO2); - initiating processing of the first display list by the graphics processor (10); - transferring a second display list from the stored program computer (14) to a second one of the plurality of the FIFOs (26, FIFO1, FIFO2); - interrupting processing of the first display list by the graphics processor (10) and storing a context of the first display list in the context memory; - initiating processing of the second display list by the graphics processor (10); - detecting completion of processing of the second display list by the graphics processor (10); - restoring the context of the first display list stored by the context memory; and - continuing processing of the first display list by the graphics processor (10).
References Cited (Backward Citations)
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