Synchronous method and apparatus for processors

Claim 2

A synchronous apparatus according to claim 1, wherein said local synchronization circuit (50n) includes for each of the processors in said group: means (200) for detecting an access request signal issued from an associated processor to said data sharing circuit; and logic means (208, 211) for operating a logical OR of an output of said access request detecting means and said status signal and generating a ready signal for extending the termination of a bus cycle to said associated processor when said status signal has not been generated and said access request signal has been generated.

Claim 3

A synchronous apparatus according to claim 1, wherein said synchronous processing circuit (101) includes for each of said processors: synchronous registers (UB0 - UBn; 5) each for storing bit information outputted from an associated processor for designating processors in a group to which said associated processor belongs; means (UC0 - UCn, UA0 - UAn, SℓD0 - SℓDn; 6, 7, 8) for cancelling the designation in said bit information corresponding to a processor in said group when said processor has terminated a related task processing; means (UD0; 6) coupled to said cancelling means for detecting, on the basis of the state of said bit information, that all of the processors in said group have terminated task processings; means (UB0 - UBn, Tℓ0 - Tℓn; 7, Tℓ0 - Tℓn) coupled to receive a signal from said detecting means indicating that all of the processors in said group have terminated the task processings to supply a synchronication termination signal to said associated processor; and means (UB0 - UBn, UA0 - UAn, UD0, 6, 7, 8) coupled to receive the signal from said detecting means indicating that all of the processors in said group have terminated task processings to restore said synchronous register to an initial state.

Claim 4

A synchronous apparatus according to claim 3, wherein said synchronous processing circuit (101) includes a single flip-flop means (7) for each of said processors, said flip-flop means having: a trigger clock input terminal responsive to a storing operation for storing said bit information to said synchronous register to be triggered; an input terminal ( PR ¯ ) for inputting the signal from said detecting means, said signal indicating that all of the processors in said group have terminated task processings; a first output terminal (Q) responsive to a trigger to said trigger terminal to generate an output for cancelling a designation in said bit information stored in said synchronous register corresponding to said associated processor as well as responsive to a signal inputted to said input terminal ( PR ¯ ) to restore said bit information in said synchronous register to the initial state; and a second output terminal ( Q ¯ ) responsive to the signal inputted to said input terminal ( PR ¯ ) to output said synchronization termination signal to said associated processor.

Claim 5

A synchronous method for a plurality of processors which share a plurality of tasks and parallelly process the shared tasks, comprising the steps of: outputting from each of said processors bit information for designating a processor in a group to which an associated processor belongs, upon terminating a task processing under execution, and storing said bit information in a synchronous register (UB0 - UBn; 5) provided in each of said processors; cancelling the designation corresponding to said associated processor in said bit information stored in all of said synchronous registers in the processors by each of said processors at the time each of said processors has terminated a task processing (UC0 - UCn, UA0 - UAn, SℓD0 - SℓDn; 6, 7, 8); detecting for each of said processors that all of processors in a group to which said associated processor belongs have terminated task processings on the basis of the state of the bit information in said related synchronous register (UD0; 6); providing said associated processor with a synchronization termination signal when all of the processors in said group have terminated the task processings (UB0 - UBn, Tℓ0 - Tℓn; 7, Tℓ0 - Tℓn); detecting, in each of said processors, an access request signal generated from said associated processor to a data sharing circuit (102) for holding data shared among said processors (200); and generating, in each of said processors, a ready signal for extending the termination of a bus cycle to said associated processor when all of the processors in said group to which said associated processor belongs have not terminated all task processings and said access request signal has been generated (208, 211).

Claim 6

A synchronous method according to claim 5 further comprising the step of restoring, in each of said processors, all of said sycnhronous registers in said group to an initial state when all of the processors in said group to which said associated processor belongs have terminated the task processings (UB0 - UBn, UA0 - UAn, UD0; 6, 7, 8).

Claim 7

A synchronous processing system for synchronously processing a plurality of processors and controlling a parallel processing without contradiction to necessary processing sequence comprising: means for instructing an output of active task termination information corresponding to said each processor at the time said each processor has terminated a task thereof; means for resetting said active task termination information corresponding to said each processor to an inactive state, when task termination information from processors which should be synchronized has become all active, using the information at this time; and means for recognizing the termination of a synchronous processing by examining said task termination information by the processors.

Claim 8

A synchronous processing system for processors according to claim 7 including an instruction (EO instruction) for instructing an output of processor-active task termination information and an instruction (W instruction) for recognizing the termination of a synchronous processing.

Claim 9

A synchronous processing system for processors according to claim 8, wherein: if, at the time one processor has terminated a task, there is no relation from a task which has been executed by another processor and terminated at the same level as the task terminated by said one processor to a task which is to be next executed by said one processor, the EO instruction for only outputting the task termination information is inserted, and if said one processor, when proceeding to the next task after having terminated a task, does not require information from other processors which have executed tasks at the same level, said one processor executes the EO instruction to unconditionally progress the processing to the next task.

Claim 10

A synchronous processing system for processors, wherein one processor which has executed the EO instruction at the preceding synchronous level to proceed to a task processing presently under execution, if a task to be next executed at the time of the termination of the task has a relation with a task which is to be executed by another processor and terminated at the same level, executes the W instruction as a synchronization examining instruction corresponding to the EO instruction which has been executed at the preceding level, and thereafter a synchronous processing is performed at the present synchronous level to progress the processing to the next task.