Patent EP0475269A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0475269A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Integrated circuit device comprising a wiring substrate

Assignee: Hitachi Ltd
•
Filing: 1991-09-04
•
Granted: —
•
Expires: 2011-09-04
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract This invention discloses an integrated circuit device (100) including an integrated circuit chip (1) having logic circuits (10, 10', 11, 11') formed therein and a wiring substrate (2) for mounting thereon the integrated circuit chip, having therein signal wirings (5) for connecting mutually input terminals (6') and output terminals (6) of the integrated circuit chip. The integrated circuit device includes signal wirings (5) for connecting the input terminals (6') and output terminals (6) of the same integrated circuit chip inside the wiring substrate. The logic circuits inside the same integrated circuit chip are mutually connected by signal wirings (12, 13, 13') inside the integrated circuit chip when a wiring length is small, and by signal wirings (5) inside the wiring substrate when the wiring length is great.

Inventors

  • 👤 Keiichirou Nakanishi
  • 👤 Minoru Yamada
  • 👤 Tatsuya Hitachi Daini Kyoshinryo Saitoh
  • 👤 Kazumichi Hitachi Koyasudai Apato C-405 Yamamoto

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 23:13
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W44/00; H10W44/401; H10W70/67; H10W70/68; H10W70/685; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 111 words
An integrated circuit device (100) comprising: an integrated circuit chip (1) having a plurality of logic circuits (10, 10', 11, 11') formed therein; output terminals (6) for taking out output signals of said logic circuits from said integrated circuit chip; input terminals (6') for taking input signals to said logic circuits into said integrated circuit chip; a wiring substrate (2) for mounting thereon said integrated circuit chip; and signal wirings (5) inside said substrate, disposed in said wiring substrate, for connecting electrically said output terminals to said input terminals; whereby mutual connection between said logic circuits inside the same integrated circuit chip is made through said wiring inside said wiring substrate.
Claim 2
Dependent Claim 40 words
An integrated circuit device according to claim 1, wherein said wiring inside said wiring substrate is formed inside said wiring substrate and is connected to said output terminals and said input terminals through through-holes (4, 4') inside said wiring susbstrate.
Claim 3
Dependent Claim 29 words
An integrated circuit device according to claim 1, wherein said wiring inside said wiring substrate is connected to a termination resistor (9) on the side of said input terminal.
Claim 4
Dependent Claim 26 words
An integrated circuit device according to claim 3, wherein the output signal from said logic circuit is connected to said output terminal through a buffer circuit.
Claim 5
Dependent Claim 25 words
An integrated circuit device according to claim 1, wherein said integrated circuit chip has a size substantially equal to the size of a semiconductor wafer.
Claim 6
Dependent Claim 122 words
An integrated circuit device (100) comprising: an integrated circuit chip (1) having a plurality of logic circuits (10, 10', 11, 11') formed therein; first signal wirings (12, 13, 13') disposed inside said integrated circuit chip; output terminals (6) for taking out output signals of said logic circuits from said integrated circuit chip; input terminals (6') for taking input signals to said logic circuits into said integrated circuit chip; a wiring substrate (2) for mounting thereon said integrated circuit chip; and second signal wirings (5) disposed on said wiring substrate, for connecting electrically said output terminals to said input terminals; wherein said logic circuits inside said integrated circuit chip are mutually connected by either said first signal wirings or said second signal wirings.
Claim 7
Dependent Claim 39 words
An integrated circuit device according to claim 6, which further comprises: first termination resistors connected to the near-end side of said first signal wirings; and second termination resistors (9) connected to the far-end side of said second signal wirings.
Claim 8
Dependent Claim 26 words
An integrated circuit device according to claim 7, wherein the wiring length between said logic circuits by said first signal wirings is up to 5 cm.
Claim 9
Dependent Claim 23 words
An integrated circuit device according to claim 8, wherein said second signal wiring has a greater wiring length than said first signal wiring.
Claim 10
Dependent Claim 24 words
An integrated circuit device according to claim 7, wherein said first termination resistor is formed by use of resistance made by a diffusion process.
Claim 11
Dependent Claim 25 words
An integrated circuit device according to claim 6, wherein said integrated circuit chip has a size substantially equal to the size of a semiconductor wafer.
Claim 12
Dependent Claim 96 words
A connection method of logic circuits in an integrated circuit device (100) including an integrated circuit chip (1) having a plurality of logic circuits (10, 10', 11, 11') formed therein and a wiring substrate (2) for mounting thereon said integrated circuit chip, comprising the steps of: connecting mutually said logic circuits having a distance below a predetermined wiring length by first signal wirings (12, 13, 13') disposed inside said integrated circuit chip; and connecting mutually said logic circuits having a distance exceeding said predetermined wiring length by second signal wirings (5) disposed inside said wiring substrate.
Claim 13
Dependent Claim 87 words
A connection method of connecting mutually logic circuits in an integrated circuit device according to claim 12, wherein the connection using said second signal wirings is made by connecting the outputs of said logic circuits to said second signal wirings through output terminals (6) of said integrated circuit chip and through through-holes (4) inside said wiring substrate and connecting the inputs of said logic circuits to said second signal wirings through input terminals (6') of said integrated circuit chip and through through-holes (4') inside said wiring substrate.
Claim 14
Dependent Claim 51 words
A connection method of connecting mutually logic circuits in an integrated circuit device according to claim 12, wherein said predetermined wiring length is such that the delay time of signal transmission by said first signal wirings is substantially equal to the delay time of signal transmission by said second signal wirings.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag