Method of fabricating integrated circuit chip package

Claim 1

A method of fabricating an integrated circuit chip package forming a multi-chip module including the steps of electrically connecting a plurality of IC chips each having in one surface thereof a plurality of predetermined impurity diffusion regions and in said one surface a plurality of metal bumps connected selectively to said impurity diffusion regions, respectively, to a single, flat silicon circuit board having in at least a portion of its surface a predetermined wiring pattern through said metal bumps by means of flip-chip interconnection, comprising the steps of: forming a first flat film of an organic insulating material on said one surfaces of said IC chips up to a first thickness; forming a plurality of through-holes in said film at predetermined positions and forming said metal bumps through said through-holes; forming a second flat film of an organic insulating material on a surface of said silicon circuit substrate up to a second thickness; forming in said first film a plurality of through-holes each having a wall surface discontinuity in periphery, at positions corresponding to said metal bumps of said IC chips; filling said through-holes with solder metal, respectively; forming at least one of said first film and said second film with adhesive of thermosetting organic insulating material; and heating said silicon circuit board with said metal bumps being mated with said through-holes to melt said solder metal and to thermoset said adhesive.