Patent EP0475118A2 successfully refreshed from Google Patents.
EP0475118A2
Expired / Lapsed
EP
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Current mirror amplifier circuit and method of driving the same
Assignee: Fujitsu VLSI Ltd
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Filing: 1991-08-16
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Granted: —
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Expires: 2011-08-16
Abstract
Abstract A current mirror amplifier circuit includes a differential amplifier circuit (1) having first and second nodes (A, B) for differentially amplifying a pair of complementary input signals in an activation mode, a current mirror circuit (2) coupled between a first power source (Vcc) and the first and second nodes of the differential amplifier circuit, a switching circuit (3) coupled between the differential amplifier circuit and a second power source (GND) which supplies a second voltage lower than a first voltage supplied by the first power source for switching a mode of the differential amplifier circuit from a standby mode to the activation mode in response to an activation signal, and a circuit (4) coupled between the first power source and the first and second nodes of the differential amplifier circuit for pulling up potentials of the first and second nodes during the standby mode, where this circuit is deactivated after the differential amplifier circuit is switched from the standby mode to the activation mode.
Inventors
- 👤 Yoshiharu Kato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 06:29
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/72
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
192 words
A current mirror amplifier circuit for generating a pair of complementary output signals comprising: differential amplifier circuit means (1), having first and second nodes (A, B), for differentially amplifying a pair of complementary input signals in an activation mode; current mirror circuit means (2) coupled between a first power source (Vcc) and the first and second nodes of said differential amplifier circuit means; and switching circuit means (3), coupled between said differential amplifier circuit means and a second power source (GND) which supplies a second voltage lower than a first voltage supplied by the first power source, for switching a mode of said differential amplifier circuit means from a standby mode to the activation mode in response to an activation signal, characterized in that there is provided: first circuit means (4), coupled between the first power source (Vcc) and the first and second nodes (A, B) of said differential amplifier circuit means (1), for pulling up potentials of the first and second nodes (A, B) during the standby mode, said first circuit means being deactivated after the differential amplifier circuit means (1) is switched from the standby mode to the activation mode.
Claim 2
Dependent Claim
27 words
The current mirror amplifier circuit as claimed in claim 1, characterized in that the control signal is delayed by a predetermined time relative to the activation signal.
Claim 3
Dependent Claim
47 words
The current mirror amplifier circuit as claimed in claim 1 or 2, characterized in that there is further provided control signal output circuit means (5) for generating the control signal based on the activation signal and for supplying the control signal to said first circuit means (4).
Claim 4
Dependent Claim
217 words
The current mirror amplifier circuit as claimed in claim 1, characterized in that said differential amplifier circuit means (1) includes: a first transistor (T1) having a gate which receives one of the complementary input signals and a drain which is connected to the first node (A), and a second transistor (T2) having a gate which receives the other of the complementary input signals and a drain which is connected to the second node (B), sources of the first and second transistors being coupled in common to said switching circuit means (3), said current mirror circuit means (2) includes: a third transistor (T4) having a source which is coupled to the first power source (Vcc) and a drain which is coupled to the first node (A), and a fourth transistor (T5) having a source which is coupled to the first power source and a drain which is coupled to the second node (B), gates of the third and fourth transistors being coupled in common to the second node, and said switching circuit means (3) includes: a fifth transistor (T3) having a gate which receives the activation signal and a source and a drain which are respectively coupled to the second power source (GND) and the sources of the first and second transistors within said differential amplifier circuit means.
Claim 5
Dependent Claim
49 words
The current mirror amplifier circuit as claimed in claim 4, characterized in that said current mirror circuit means (2) includes a sixth transistor (T6) which is coupled in parallel to the third transistor (T4), and a seventh transistor (T7) which is coupled in parallel to the fourth transistor (T5).
Claim 6
Dependent Claim
54 words
The current mirror amplifier circuit as claimed in claim 4 or 5, characterized in that the first, second and fifth transistors (T1, T2, T3) are N-channel MOS transistors, the third and fourth transistors (T4, T5) are P-channel MOS transistors, the first voltage is a positive voltage and the second voltage is a ground voltage.
Claim 7
Dependent Claim
31 words
The current mirror amplifier circuit as claimed in any of claims 4 to 6, characterized in that the control signal is delayed by a predetermined time relative to the activation signal.
Claim 8
Dependent Claim
43 words
The current mirror amplifier circuit as claimed in claim 7, characterized in that the control signal is generated at a time when a potential at the second node (B) becomes a threshold voltage of the fourth transistor (T5) lower than the first voltage.
Claim 9
Dependent Claim
93 words
The current mirror amplifier circuit as claimed in any of claims 4 to 8, characterized in that there is further provided control signal output circuit means (5) for generating the control signal based on the activation signal and for supplying the control signal to said first circuit means (4), said control signal output circuit means including a delay circuit (R1, C) for generating the control signal by delaying the activation signal by a predetermined time so that the control signal is generated before potentials at the first and second nodes (A, B) saturate.
Claim 10
Independent Claim
222 words
A method of driving a current mirror amplifier circuit which comprises differential amplifier circuit means (1), having first and second nodes (A, B), for differentially amplifying a pair of complementary input signals in an activation mode; current mirror circuit means (2) coupled between a first power source (Vcc) and the first and second nodes of said differential amplifier circuit means; switching circuit means (3), coupled between said differential amplifier circuit means and a second power source (GND) which supplies a second voltage lower than a first voltage supplied by the first power source, for switching a mode of said differential amplifier circuit means from a standby mode to the activation mode when activated in response to an activation signal; and first circuit means (4), coupled between the first power source and the first and second nodes of said differential amplifier circuit means, for pulling up potentials of the first and second nodes (A, B) during the standby mode, characterized in that said method comprises the steps of: (a) supplying the complementary input signals to said differential amplifier circuit means (1) and the activation signal to said switching circuit means (3); and (b) supplying the control signal to said first circuit means (4) after a predetermined time elapses from a time when said switching circuit means (3) is activated by the activation signal.
Claim 11
Dependent Claim
132 words
The method of driving the current mirror amplifier circuit as claimed in claim 10, characterized in that said current mirror circuit means (2) includes a first transistor (T4) having a source which is coupled to the first power source (Vcc) and a drain which is coupled to the first node (A), and a second transistor (T5) having a source which is coupled to the first power source and a drain which is coupled to the second node (B), gates of the first and second transistors being coupled in common to the second node, and said step (b) supplies to said first circuit means (4) the control signal at a time when a potential at the second node (B) becomes a threshold voltage of the second transistor (T5) lower than the first voltage.
Claim 12
Dependent Claim
53 words
The method of driving the current mirror amplifier circuit as claimed in claim 10 or 11, characterized in that said step (b) generates the control signal by delaying the activation signal by a predetermined time so that the control signal is generated before potentials at the first and second nodes (A, B) saturate.
References Cited (Backward Citations)
No citation records indexed.
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