Patent EP0474450A2 successfully refreshed from Google Patents.
EP0474450A2
Expired / Lapsed
EP
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Processor system with improved memory transfer means
Assignee: International Business Machines Corp
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Filing: 1991-09-02
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Granted: —
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Expires: 2011-09-02
Abstract
Abstract This disclosure describes an efficient method of moving data from one location in memory to another without caching the data. This includes data transfers from one main storage location to another, transfers between main and expanded storage, and transfers from one expanded storage location to another.
Inventors
- 👤 Robert Dov Herzl
- 👤 Kenneth Anthony Lauricella
- 👤 Linda Legault Quinn
- 👤 David Andrew Schroter
- 👤 Allan Rowe Steel
- 👤 Joseph Lester Temple Iii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 16:15
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0822; G06F12/0888; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
63 words
A processor system comprising: a memory having multiple memory locations, a processor with a store-in cache, said processor providing request signals, a store buffer coupled between said store-in cache and said memory, said store buffer being responsive to a processor's request for the transfer of data from one memory location to another for holding data between transfers without passing through said store-in cache.
Claim 2
Dependent Claim
34 words
The combination of Claim 1 wherein said memory includes a main store and an expanded storage and said one memory location is a main storage location and said another is an expanded storage location.
Claim 3
Dependent Claim
22 words
The combination of Claim 1 wherein said processor request is for a page transfer and said store buffer holds the paging data.
Claim 4
Dependent Claim
16 words
The combination of Claim 1 wherein said store buffer also holds LRU castouts and XI castouts.
Claim 5
Independent Claim
87 words
A method of transferring data from one location in memory to a second location under control of a processor in a multiprocessor system without going through the processors cache comprising the steps of: fetching line by line the data from said one location under said processor's microcode, storing the fetched lines line by line in a store buffer which is not cached, and storing the line of data line by line into said second location under said microcode program control without passing through said processors own cache
Claim 6
Dependent Claim
27 words
The method of Claim 5 wherein said one memory location is main store or expanded store and said second location is expanded store or main store respectively.
Claim 7
Dependent Claim
15 words
The method of Claim 6 wherein said store buffer also holds LRU and XI castouts.
Claim 8
Independent Claim
166 words
A method of transferring a page of data from one location to a second location in memory under control of a processor in a multiprocessor system without going through the processor's cache where said system includes a store buffer coupled between a processor's cache and memory for holding LRU castouts and XI castouts comprising the steps of: a) checking for any LRU or XI castouts in progress, b) holding the paging transfer until LRU or XI castouts are complete if LRU or XI is in progress, c) locking out all new castouts from occuring until paging transfer is complete if none are in progress when paging transfer is requested, d) fetching line by line the data from said one location under said processors microcode, e) storing the fetched lines line by line in a store buffer which is not cached, and f) storing the line of data line by line into said second location under said microcode program control without passing through said processors own cache.
References Cited (Backward Citations)
No citation records indexed.
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