EP0474289A1
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EP
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A method for the fabrication of low leakage polysilicon thin film transistors
Assignee: Koninklijke Philips NV
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Filing: 1991-08-28
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Granted: —
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Expires: 2011-08-28
Abstract
Abstract According to one aspect of the invention thin film transistors exhibiting a reduced reverse leakage current are manufactured according to a method which includes the following steps: Depositing a relatively thick layer of silicon oxide on a substrate by chemical vapor deposition, depositing a relatively thin polysilicon layer, annealing the relatively thin polysilicon layer at a temperature of less than 650°C in a nitrogen atmosphere to cause large grain formation, forming islands by etching the thin polysilicon layer, forming a thin gate oxide layer on at least one of the islands by oxidation under high pressure at a temperature below 650°C, depositing a relatively thick doped polysilicon layer on the gate oxide layer, forming a gate from the, relatively heavily doped, relatively thick polysilicon layer while having exposed laterally adjacent areas of the gate oxide layer and the underlying polysilicon island, lightly doping portions of the resultant exposed areas of the island of polysilicon laterally adjacent to the gate to form lightly doped source and drain areas, depositing a thin layer of silicon oxide on the gate and lightly doped source and drain areas, relatively heavily doping exposed areas of the layer of polysilicon laterally adjacent to the lightly doped source and drain areas to form relatively heavily doped source and drain areas, annealing the source and drain areas at a temperature of 600°C to 750°C and then hydrogenating the resultant device at a temperature of less than about a 400°C with the hydrogen plasma.
Inventors
- 👤 Udayanath Mitra
- 👤 Mahalingam Venkatesan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 04:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10P; H10P36/00; H10P36/03; H10P95/00; H10P95/40; H10P95/402; Y; Y10; Y10S; Y10S148/00; Y10S148/15
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
296 words
A low temperature method of manufacturing a thin film transistor having a low leakage current, said method comprising: a) depositing a thin layer of an alkali-inert inorganic material on a glass substrate having an annealing point less than 650°C, b) depositing a first relatively thick layer of silicon oxide on the layer of inorganic material by chemical vapor deposition, c) depositing a relatively thin amorphous silicon layer, at a temperature of 520-570°C, on the first layer of silicon oxide, d) annealing said relatively thin amorphous silicon layer at a temperature of less than 650°C in a nitrogen atmosphere, to form a large grain polysilicon layer, e) etching said relatively thin polysilicon layer to remove portions of said polysilicon layer and expose selected areas of said first layer of silicon oxide and form islands in said polysilicon layer, f) oxidizing at least one of said islands under high pressure at a temperature below 650°C to form a thin gate oxide layer on said island(s) of polysilicon, g) depositing a relatively thick, heavily doped polysilicon layer on said gate oxide layer and etching away portions of said relatively heavily doped polysilicon layer to form a gate, h) relatively lightly implanting p or n dopants in areas of said island of polysilicon laterally adjacent to said gate to form lightly doped source and drain areas, i) providing by chemical vapor deposition a second relatively thin layer of silicon oxide on said gate and on adjacent lightly doped source and drain areas, j) relatively heavily doping areas of said first layer of silicon adjacent to said relatively lightly doped source and drain areas, k) annealing said source and drain areas at a temperature below 650°C, and l) hydrogenating the resultant device at a temperature of 200-400°C with a hydrogen plasma.
Claim 2
Dependent Claim
13 words
The method of Claim 1 wherein the alkali-inert inorganic material is silicon nitride.
Claim 3
Dependent Claim
15 words
The method of Claim 2 wherein the substrate has an annealing point of about 550-650°C.
Claim 4
Dependent Claim
18 words
The method of Claim 3 wherein said relatively thick polysilicon layer is annealed at a temperature of 580-620°C.
Claim 5
Dependent Claim
24 words
The method of Claim 4 wherein the gate oxide layer is formed by heating the island at 550-650°C at a pressure of 5-50 atmospheres.
Claim 6
Independent Claim
279 words
A method of manufacturing a thin film transistor exhibiting a reduced reverse leakage current, said method comprising: a) forming a first relatively thick layer of silicon oxide on a semiconductor substrate, b) depositing a relatively thin polysilicon layer at a temperature of less than 650°C on said first layer of silicon oxide, c) annealing said relatively thin polysilicon layer in a nitrogen atmosphere, d) removing, by etching, selective portions of said relatively thin polysilicon layer to expose selective portions of said first layer of silicon oxide and forming islands in said relatively thin polysilicon layer, e) oxidizing at least one of said islands under high pressure at a temperature below about 650°C to form a thin gate oxide layer on said island(s) of said relatively thin polysilicon layer, f) depositing a second relatively thick polysilicon layer on said gate oxide layer, g) heavily doping said second polysilicon layer and etching away, by reactive ion etching, portions of the resultant doped second polysilicon layer to form a gate, h) relatively lightly doping resultant exposed areas of said island of said layer of polysilicon laterally adjacent to said gate to form lightly doped source and drain areas, i) providing a relatively thin, layer of silicon oxide on said gate and on said adjacent lightly doped source and drain areas, j) relatively heavily doping exposed areas of said island of said layer of polysilicon adjacent to said lightly doped source and drain areas to form relatively heavily doped source and drain areas, k) annealing said source and drain areas at a temperature of 600-750°C, and l) hydrogenating the resultant device at a temperature of less than about 400°C with a hydrogen plasma.
Claim 7
Dependent Claim
31 words
The method of Claim 6 wherein said high pressure oxidation of said island is carried out at a temperature of 550 - 650°C under a pressure of 5 - 50 atmospheres.
Claim 8
Dependent Claim
14 words
The method of Claim 7 wherein the device is hydrogenated at 200 - 450°C.
Claim 9
Dependent Claim
14 words
The method of Claim 8 wherein the second polysilicon layer is doped with BF₃.
Claim 10
Dependent Claim
35 words
The method of Claim 8 wherein said first polysilicon layer has a thickness of about 500 Å to 1500 Å and said second polysilicon layer has a thickness of about 4000 Å to 7000 Å.
Claim 11
Dependent Claim
20 words
The method of Claim 1 wherein the first, relatively thick, layer of silicon oxide is deposited by chemical vapor deposition.
Claim 12
Dependent Claim
20 words
The method of Claim 2 wherein the first, relatively thick, layer of silicon oxide is deposited by chemical vapor deposition.
Claim 13
Dependent Claim
31 words
The method of Claim 5 wherein the thin layer of silicon nitride has a thickness of 800-1200Å and the relatively thick silicon oxide layer has a thickness of 17,000 - 23,000Å.
Claim 14
Dependent Claim
196 words
A thin film transistor exhibiting a low leakage current upon reverse biasing said transistor comprising a) a glass substrate having an annealing point greater than 650°C, b) a relatively thin layer of an alkali-inert inorganic material deposed on said substrate, c) a first relatively thick layer of silicon oxide deposed on said alkali-inert inorganic material, d) a first relatively thin polysilicon layer deposed on said first relatively thick layer of silicon oxide, e) a relatively thin gate oxide deposed on said first relatively thin polysilicon layer, f) a gate, provided by a relatively heavily doped area, g) a second relatively thick polysilicon layer provided on a portion of the surface of said gate oxide layer, h) relatively lightly doped source and drain areas provided in portions of said first relatively thin layer of polysilicon laterally adjacent to said gate, i) a relatively thin silicon oxide layer provided on said gate and on said lightly doped source and drain areas, j) relatively heavily doped source and drain areas provided in portions of said first relatively thin layer of polysilicon laterally adjacent to said relatively slightly doped source and drain areas, said source and drain areas being annealed.
Claim 15
Dependent Claim
15 words
The thin film transistor of Claim 14 wherein the alkali-inert inorganic material is silicon nitride.
References Cited (Backward Citations)
EP0129037A1
Cited
US4851363A
Cited
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