Polysilicon FETs

Claim 2

1) A fifld effect transistor comprising: A channel region comprising polycrystalline semiconductor material; source and drain regions connected to said channel region; and a gate positioned to apply an electric field to said channel region between said source and drain regions; Wherein said channel has an equilibrium carrier concentration of at least 1017 per cubic centimeter.

Claim 3

2) A field effect transistor comprising: A channel region comprising polycrystalline semiconductor material; Source and drain regions connected to said channel region; and A gate positioned to apply an electric field to said channel region between said source and drain regions. Wherein said channel has an equilibrium carrier concentration of at least five times 10 16 per cubic centimeter; and Wherein said channel is less than 3000 Angstroms thick.

Claim 4

3) A field effect transistor comprising: A channel region comprising polycrystalline semiconductor materrial; Source and drain regions connected to said channel region; and A gate positioned to apply an electric field to said channel region between said source and drain regions; Wherein said channel has an equilibrium carrier concentration of at least five times 10 16 per cubic centimeter.

Claim 5

4) A field effect transistor comprising: a channel region comprising polycrystalline semiconductor material; source and drain regions connected to said channel region; and a gite positioned to apply an electric field to said channel region between said source and drain regions; wherein said channel has an equilibrium carrier concentration of at least 1017 per cubic centimeter, and a thickness less than 2000 Angstroms.

Claim 6

A field effect transistor comprising: a channel region comprising polycrystalline semiconductor material; source and drain regions connected to said channel region; and a gate positioned to apply an electric field to said channel region between saidd source and drain regions; wherein said channel has an equilibrium carrier concentration of at least five times 1016 per cubic centimeter, and is of the same conductivity type as said source and drain regions; wherein said channel is sufficiently thin to be depleted at zero applied gate voltage.

Claim 7

A field effect transistor comprising: a channel region comprising polycrystalline semiconductor material; source and drain regions connected to said channel region; and a gate positioned to apply an electric field to said channel region between said source and drain regions; wherein said channel has an equilibrium carrier concentration of a t least five times 1016 per cubic centimeter, and has the same conductivity type as said source and drain regions.

Claim 8

7) The transistor of Claim 1 wherein said polycrystalline material comprises polysilicon.

Claim 9

8) The transistor of Claim 2 wherein said polycrystalline material comprises polysilicon.

Claim 10

9 ) The transistor of Claim 3 wherein said polycrystalline material comprises polysilicon.

Claim 11

10) The fransistor of Claim 4 wherein said polycrystalline material comprises polysilicon.

Claim 12

11) The transistor of Claim 5 wherein said polycrystalline material comprises polysilicon.

Claim 13

12) The transistor of Claim 6 wherein said polycrystalline material comprises polysilicon.

Claim 14

13) The transistor of Claim 7 wheein said polysilicon contains a substantial admixture of a passivating species at grain boundaries thereof.

Claim 15

14) The transistor of Claim 8 wherein said polysilicon contains a substantial admixture of a passivating species at grain boundaries thereof.

Claim 16

15) The transistor of Claim 9 wherein said polysilicon contains a substantial admixture of a passivating species at grain boundaries thereof.

Claim 17

16) The transistor of Claim 10 wherein said polysilicon contains a substantial admixture of a passivating species at grain boundaries thereof.

Claim 18

17) The transistor of Claim 11 wherein said polysilicon contains a substantial admixture of a passivating species at grain boundaries thereof.

Claim 19

18) The transistor of Claim 12 wherein said polysilicon contains a substantial admixture of a passivating species at grain boundaries thereof.

Claim 20

19) The transistor of Claim 7 wherein said gate also comprises polysilicon, said gate and channel regions being doped with the same conductivity type.

Claim 21

20) The transistor of Claim 8 wherein said gate also comprises polysilicon, said gate and channel regions being doped with the same conductivity type.

Claim 22

21) The transistor of Claim 9 wherein said gate also comprises polysilicon, said gate and channel regions being doped with the same conductivity type.

Claim 23

22) The transistor of Claim 10 wherein said gate also comprises polysilicon, said gate and channel regions being doped with the same conductivity type.

Claim 24

23) The transistor of Claim 11 wherein said gate also comprises polysilicon, said gate and channel regions being doped with the same conductivity type.

Claim 25

24) The transistor of Claim 12 wherein said gate also comprises polysilicon, said gate and channel regions being doped with the same conductivity type.