Event sequencer for automatic test equipment

Claim 2

A test system for testing an electronic circuit having a plurality of I/O leads, comprising: means for generating a global clock signal; a plurality of local sequencers, each local sequencer being coupled to one of said leads, each local sequencer including means for generating, in a test period calibrated to said global clock signal, a programmable number of signal transitions of a test signal to said I/O lead; and said local sequencers being programmable with said number of signal transitions for said plurality of local sequencers such that said local sequencers can have different numbers of transitions in any given test period.

Claim 3

The test system of claim 2 further comprising: means for generating a global time zero signal indicating the beginning of said test period; means for generating a global strobe time zero signal for collecting data at the end of said test period; and means, in each of said local sequencers, for synchronizing said test period with said global time zero signal and for providing data from said pin in response to said global strobe time zero signal.

Claim 4

The test system of claim 3 further comprising: second means for generating a global time zero signal coupled to said means for synchronizing; and second means for generating a global strobe time zero signal coupled to said means for providing data; such that separate groups of said local sequencers can receive separate global time zero and global strobe time zero signals to asynchronously and independently test different groups of said I/O leads of said circuit.

Claim 5

A local sequencer for a test system having a plurality of said local sequencers, each local sequencer being coupled to a lead of a device under test, comprising: memory means for storing the time and type of events applied to and received from said device under test and for storing offsets for said time according to said event type; adder means for adding said time from said memory, one of said offsets and an externally provided global test period offset to provide a calibrated time; means for delaying an external clock signal by said calibrated time to produce a delayed clock signal; and edge generator means, coupled to said means for delaying, for producing a test signal transition for said lead at a time indicated by said delayed clock signal.

Claim 6

The local sequencer of claim 5 wherein said memory means comprises a functional memory for storing event types, a local memory for storing event times and a calibration memory for storing said offsets.

Claim 7

The local sequencer of claim 6 wherein said local memory also stores one of (a) an event type and (b) a reference to said functional memory for every event time.

Claim 8

The local sequencer of claim 7 further comprising event type decode logic having inputs coupled to said functional memory and said local memory and an output coupled to said calibration memory.

Claim 9

The local sequencer of claim 7 wherein said local memory also stores for each event time a flag indicating whether said event is the last event in a sequence of events.

Claim 10

The local sequencer of claim 5 further comprising a register coupled to the output of said adder for storing said calibrated time, and wherein said means for delaying includes a linear delay circuit having an input coupled to an output of said register.

Claim 11

The local sequencer of claim 6 wherein said event time is defined as the time since a last event.

Claim 12

A test system for testing a circuit having a plurality of I/O leads, comprising: a plurality of first event sequencers, each first event sequencer being coupled to one of said leads, for providing first test signal transitions to said lead; and a plurality of second event sequencers, each second event sequencer being coupled to one of said leads in parallel with one of said first event sequencers, for providing second signal transitions to said lead, such that said second transitions can be provided a sooner time after one of said first transitions than said first event sequencers could provide a next test signal transition.

Claim 13

A sequencer for providing test signals to a circuit being tested, comprising: memory means for storing timing data indicating the time for each of a sequence of signal transitions and functional data indicating the state to be transitioned to for said sequence, wherein a bit of said functional data can apply to a plurality of signal transitions; decoding means, having a first input coupled to receive said timing data and a second input coupled to receive said functional data, for providing an output indicating the state and transition time of events; and driver means, coupled to said decoding means, for providing said events to said circuit.

Claim 14

The sequencer of claim 13 wherein said memory means comprises a functional memory for storing functional data, a local memory for storing said timing data and a calibration memory for storing offsets for said timing data according to said functional data.

Claim 15

The sequencer of claim 14 wherein said local memory also stores, for every event time, one of (a) functional data and (b) a reference to said functional memory.

Claim 16

The sequencer of claim 15 wherein said decoding means comprises event type decode logic having inputs coupled to said functional memory and said local memory and an output coupled to said calibration memory.

Claim 17

The sequencer of claim 15 wherein said local memory also stores for each event time a flag indicating whether said event is the last event in a sequence of events.

Claim 18

A test system for testing an integrated circuit, comprising: a global sequencer including a clock signal generator, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, means for generating a period vernier value indicating an offset from said clock signal for the start of each of a plurality of test cycles; and a plurality of local sequencers, each of said local sequencers being coupled to a separate lead of said integrated circuit, for generating, in a test period calibrated to said clock signal, a programmable number of said signal transitions, such that said local sequencers can have different numbers of transitions in any given test period, each local sequencer including edge generator means, responsive to said clock signal and said period vernier value, for generating a signal transition in a signal for said pin within a test cycle defined by said period vernier value, such that said test cycle need not be a multiple of said clock signal.

Claim 19

A test system for testing an integrated circuit, comprising: a global sequencer including a clock signal generator, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, means for generating a period vernier value indicating an offset from said clock signal for the start of each of a plurality of test cycles; and a plurality of local sequencers, each of said local sequencers being coupled to a separate lead of said integrated circuit, each local sequencer including memory means for storing timing data indicating the time for each of a sequence of signal transitions and functional data indicating the state to be transitioned to for said sequence, wherein a bit of said functional data can apply to a plurality of signal transitions, decoding means, having a first input coupled to receive said timing data and a second input coupled to receive said functional data, for providing an output indicating the state and transition time of events, edge generator means, responsive to said clock signal, said period vernier value and said timing data, for generating an edge in a signal for said pin within a test cycle defined by said period vernier value, such that said test cycle need not be a multiple of said clock signal, and driver means, coupled to said edge generator means, for providing said edges to said circuit.

Claim 20

A test system for testing an integrated circuit, comprising: a global sequencer including a clock signal generator, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, means for generating a period vernier value indicating an offset from said clock signal for the start of each of a plurality of test cycles; and a plurality of local sequencers, each of said local sequencers being coupled to a separate lead of said integrated circuit, each local sequencer including memory means for storing timing data indicating the time for each of a sequence of signal transitions and functional data indicating the state to be transitioned to for said sequence, wherein a bit of said functional data can apply to a plurality of signal transitions; decoding means, having a first input coupled to receive said timing data and a second input coupled to receive said functional data, for providing an output indicating the state and transition time of events; edge generator means, responsive to said clock signal, said period vernier value and said timing data for generating a programmable number of signal transitions in a signal for said pin within a test cycle defined by said period vernier value, such that said test cycle need not be a multiple of said clock signal and said local sequencers can have different numbers of transitions in any given test period, and driver means, coupled to said edge generator means, for providing said signal transitions to said circuit.

Claim 21

A local sequencer for a test system having a plurality of said local sequencers, each local sequencer being coupled to a lead of a device under test, comprising: a functional memory for storing event types; a local memory for storing event times, one of (a) an event type and (b) a reference to said functional memory for every event time, and a flag indicating whether said event is the last event in a sequence of events; a calibration memory for storing offsets for said event times according to said event type; event type decode logic having inputs coupled to said functional memory and said local memory and an output coupled to said calibration memory; adder means for adding said time from said memory, one of said offsets and an externally provided global test period offset to provide a calibrated time; means for delaying an external clock signal by said calibrated time to produce a delayed clock signal; and edge generator means, coupled to said means for delaying, for producing a test signal transition to said lead at a time indicated by said delayed clock signal.