Patent EP0473420A2 successfully refreshed from Google Patents.
EP0473420A2
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EP
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Virtual long instruction word memory architecture for digital signal processor
Assignee: Hitachi Ltd
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Filing: 1991-08-28
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Granted: —
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Expires: 2011-08-28
Abstract
Abstract An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no-operation instruction to generate along instruction word when the predefined criteria are not met. In that case, the second instruction may be accessed again during the next instruction fetch cycle as the first of two adjacent instructions.
Inventors
- 👤 Stephen G. Haigh
- 👤 Toru Baji
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 19:02
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/34
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
83 words
Instruction memory apparatus for a data processing unit, comprising: storage means for storing a sequence of instructions at a sequence of address locations, including means for accessing a pair of sequentially adjacent instructions, a first one of which is stored in said storage means at a specified address location; and instruction preprocessing means, coupled to said storage means, for combining said pair of sequentially adjacent instructions into a single long instruction word when said pair of instructions meet predefined criteria for being combined.
Claim 2
Dependent Claim
35 words
The instruction memory apparatus of Claim 1, said instruction preprocessing means generating a long instruction word from only said first one of said pair of sequentially adjacent instructions when said predefined criteria are not met.
Claim 3
Dependent Claim
92 words
The instruction memory apparatus of Claim 2, further including: a program counter coupled to said storage means and instruction preprocessing means, said program counter generating said specified address and including means for incrementing said specified address by a value of one when said instruction preprocessing means generates a long instruction word from only said first one of said pair of sequentially adjacent instructions, and for incrementing said specified address by a value of two when said instruction preprocessing means combines said pair of sequentially adjacent instructions into a single long instruction word.
Claim 4
Dependent Claim
54 words
The instruction memory apparatus of Claim 2, said instruction preprocessing means including means for generating a long instruction word from only said first one of said pair of sequentially adjacent instructions when said predefined criteria are not mat by combining said first instruction with a predefined no-operation instruction to form a long instruction word.
Claim 5
Dependent Claim
22 words
The instruction memory apparatus of Claim 4, said accessing means in said storage means simultaneously accessing a pair of sequentially adjacent instructions.
Claim 6
Dependent Claim
186 words
Instruction memory apparatus for a digital signal processing unit, said digital signal processing unit including a first instruction decoder for decoding register store and load instructions, and a second instruction decoder for decoding signal processing instructions, said instruction memory apparatus comprising: storage means for storing a sequence of instructions at a sequence of address locations, including means for accessing a pair of sequentially adjacent instructions, a first one of which is stored in said storage means at a specified address location; and instruction preprocessing means, coupled to said storage means, for combining said pair of sequentially adjacent instructions into a single long instruction word when said pair of instructions meet predefined criteria for being combined, and for generating a long instruction word from only said first one of said pair of sequentially adjacent instructions when said predefined criteria are not met; said predefined criteria comprising the requirement that one of said pair of sequentially adjacent instructions be an instruction selected from the set consisting of register store instructions and register load instructions, and that the other of said pair of instructions be a signal processing instructions.
Claim 7
Dependent Claim
92 words
The instruction memory apparatus of Claim 6, further including: a program counter coupled to said storage means and instruction preprocessing means, said program counter generating said specified address and including means for incrementing said specified address by a value of one when said instruction preprocessing means generates a long instruction word from only said first one of said pair of sequentially adjacent instructions, and for incrementing said specified address by a value of two when said instruction preprocessing means combines said pair of sequentially adjacent instructions into a single long instruction word.
Claim 8
Dependent Claim
22 words
The instruction memory apparatus of Claim 7, said accessing means in said storage means simultaneously accessing a pair of sequentially adjacent instructions.
Claim 9
Independent Claim
87 words
A method of storing and fetching instructions for a data processing unit, the steps of the method comprising: storing a sequence of instructions at a sequence of address locations in a memory; accessing a pair of instructions stored at sequentially adjacent address locations in said memory, a first one of said pair of instructions being stored at a specified address location in said memory; and combining said pair of instructions into a single long instruction word when said pair of instructions meet predefined criteria for being combined.
Claim 10
Dependent Claim
37 words
The method of storing and fetching instructions set forth in Claim 9, said combining step generating a long instruction word from only said first one of said pair of instructions when said predefined criteria are not met.
Claim 11
Dependent Claim
70 words
The method of storing and fetching instructions set forth in Claim 10, further including the steps of: incrementing said specified address by a value of one when said combining step generates a long instruction word from only said first one of said pair of instructions, and incrementing said specified address by a value of two when said combining step combines said pair of instructions into a single long instruction word.
Claim 12
Dependent Claim
53 words
The method of storing and fetching instructions set forth in Claim 10, said combining step generating a long instruction word from only said first one of said pair of instructions when said predefined criteria are not met by combining said first instruction with a predefined no-operation instruction to form a long instruction word.
Claim 13
Dependent Claim
23 words
The method of storing and fetching instructions set forth in Claim 12, said accessing step simultaneously accessing said pair of sequentially adjacent instructions.
Claim 14
Dependent Claim
23 words
The method of storing and fetching instructions set forth in Claim 9, said accessing step simultaneously accessing said pair of sequentially adjacent instructions.
References Cited (Backward Citations)
No citation records indexed.
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