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EP0473129A2
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Asymmetrical non-volatile memory cell, arrays and methods for fabricating same
Assignee: Texas Instruments Inc
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Filing: 1991-08-28
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Granted: —
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Expires: 2011-08-28
Abstract
Abstract A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).
Inventors
- 👤 David K. Liu
- 👤 Man Wong
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 11:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10B; H10B41/00; H10B41/30; H10D30/60; H10D30/601; H10D30/603; H10D30/605; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10B69/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
117 words
A non-volatile memory cell formed in a face of a layer of semiconductor of a first conductivity type, comprising: first and second heavily doped diffused regions formed in said layer of semiconductor to be of a second conductivity type opposite said first conductivity type, said first and second highly doped diffused regions spaced by a channel area; a lightly doped diffused region formed in said layer of semiconductor to be of said second conductivity type, said lightly doped diffused region formed adjacent said second heavily doped diffused region; a floating gate conductor insulatively overlying said channel area and insulatively overlying said lightly doped diffused region; and a control gate conductor capacitively coupled with said floating gate conductor.
Claim 2
Dependent Claim
23 words
The memory cell of Claim 1, and further comprising a second lightly doped diffused region formed adjacent said first heavily doped diffused region.
Claim 3
Dependent Claim
18 words
The memory cell of Claim 2, wherein said lightly doped diffused regions are formed in said channel area.
Claim 4
Dependent Claim
31 words
The memory cell of Claim 2, wherein the dopant concentration of said first lightly doped diffused region is substantially lower than the dopant concentration of said second lightly doped diffused region.
Claim 5
Dependent Claim
21 words
The memory cell of Claim 1, wherein a terminal of said floating gate insulatively overlies said first lightly doped diffused region.
Claim 6
Dependent Claim
26 words
The memory cell of Claim 1, wherein said first heavily doped region comprises a source region and said second heavily doped region comprises a drain region.
Claim 7
Dependent Claim
28 words
The memory cell of Claim 1, wherein: said semiconductor layer comprises p-type material; said heavily doped regions comprise n-type material; and said lightly doped region comprises n-type material.
Claim 8
Dependent Claim
139 words
A non-volatile memory cell formed in a face of a layer of semiconductor of a first conductivity type, comprising: a source region formed in said face to be of a second conductivity type opposite said first conductivity type; a drain region formed in said face to be of said second conductivity type and spaced from said source region by a channel area; a first lightly doped diffused region formed in said channel area adjacent said source region to be of said second conductivity type; a second lightly diffused region formed in said channel area adjacent said drain region to be of said second conductivity type; a floating gate conductor having a first portion insulatively adjacent said channel area and a second portion insulatively adjacent said second lightly diffused region; and a control gate conductor insulatively adjacent said floating gate.
Claim 9
Dependent Claim
35 words
The memory cell of Claim 8, wherein: said source region and said drain region comprise n+ material; said first and second lightly doped diffused regions comprises n- material; and said semiconductor layer comprises p- material.
Claim 10
Dependent Claim
30 words
The memory cell of Claim 8 wherein the dopant concentration of said first lightly doped diffused region is less than the dopant concentration of said second lightly doped diffused region.
Claim 11
Dependent Claim
116 words
A field effect transistor non-volatile memory cell formed in a layer of p-type semiconductor comprising: a source including a heavily doped portion of n-type material and a lightly doped portion of n-type material, said lightly doped portion adjacent a channel area of said cell; a drain spaced from said source by said channel area, said drain including a heavily doped portion of n-type material and a lightly doped portion of n-type material, said lightly doped portion adjacent said channel area; a floating gate conductor having a first portion insulatively adjacent said channel area and a second terminal portion insulatively adjacent said lightly-doped portion of said drain; and a control gate conductor insulatively adjacent said floating gate.
Claim 12
Dependent Claim
135 words
An array of asymmetrical, non-volatile memory cells formed in columns and in rows at an angle to the columns, at a face of a layer of semiconductor of a first conductivity type, comprising: a plurality of elongated heavily doped diffused regions spaced by a plurality of elongated channel areas, a pair of said diffused regions and a respective said channel area forming a column of cells; first and second lightly diffused regions on opposite sides of each channel area and adjacent respective ones of said heavily doped diffused regions; for each cell, a floating gate insulatively adjacent a respective portion of said channel and insulatively adjacent a selected one of said lightly doped diffused regions comprising said cell; and for each row, an elongated control gate conductor, insulatively adjacent said floating gates in said row.
Claim 13
Dependent Claim
23 words
The array of Claim 12, wherein said heavily doped diffused regions comprise n+ material and said lightly doped diffused regions comprise n- material.
Claim 14
Dependent Claim
22 words
The array of Claim 12, wherein a terminal of said floating gates is formed insulatively adjacent said selected lightly doped diffused regions.
Claim 15
Independent Claim
229 words
A method for fabricating an asymmetrical non-volatile memory cell in a face of a layer of semiconductor of a first conductivity type, comprising the steps of: forming a first layer of conductor insulatively adjacent said layer of semiconductor; forming a second layer of conductor insulatively adjacent said first layer of conductor; performing an etch to define a stack including a floating gate conductor insulatively adjacent a channel area of said semiconductor and a control gate conductor insulatively adjacent said floating gate conductor, said stack having edges bordered by respective source and drain areas of said layer of semiconductor; forming a first lightly doped diffused region in said source area, and a second lightly doped diffused region in said drain area, said first and second lightly doped diffused regions formed of a second conductivity type opposite said first conductivity type and formed in alignment with said edges of said stack; forming a third lightly doped diffusion region of said second conductivity type in said drain area, said third lightly doped diffused region formed so as to extend under an adjacent one of said edge of said stack; forming sidewall insulators on said edges of said stack; and forming a heavily doped source region in said source area and a heavily doped drain region in said drain area, said source and drain regions formed to be of said second conductivity type.
Claim 16
Dependent Claim
33 words
The method of Claim 15, wherein said first and second lightly doped diffused regions are formed by an implant into said face of said layer of semiconductor at a substantially perpendicular angle thereto.
Claim 17
Dependent Claim
28 words
The method of Claim 16, wherein said third lightly doped diffused region is formed by an implant into said face of said semiconductor at a non-perpendicular angle thereto.
Claim 18
Dependent Claim
27 words
The method of Claim 17, wherein said non-perpendicular angle is in the range of 7 to 45° with respect to said face of said layer of semiconductor.
Claim 19
Dependent Claim
27 words
The method of Claim 18, wherein said layer of semiconductor is p-type semiconductor material, and said lightly doped diffused regions are formed by an implant of phosphorus.
Claim 20
Dependent Claim
32 words
The method of Claim 19, wherein said source and said drain regions are formed by an implant of arsenic into said face of said layer of semiconductor at a substantially perpendicular angle.
References Cited (Backward Citations)
No citation records indexed.
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