Phase locked loop circuit and semiconductor integrated circuit using the phase locked loop circuit

Claim 2

The phase locked loop circuit as claimed in claim 1, characterized in that said feedback loop circuit (4, 5, 10) includes a lowpass filter (4) which is coupled between an output end of said phase comparator means (2, 3) and an input end of said voltage controlled oscillator (5).

Claim 3

The phase locked loop circuit as claimed in claim 2, characterized in that said phase comparator means (2, 3) includes a phase comparator (2) which compares the phases of the input signal and the feedback signal and a charge pump (3) which outputs a boosted signal which is dependent on a phase error between the two compared signals, said boosted signal output from said charge pump being supplied to said lowpass filter (4), and said feedback loop circuit (4, 5, 10) further includes dividing means (10) for frequency-dividing the output oscillation frequency of said voltage controlled oscillator (5) and supplying a frequency divided signal to said phase comparator as the feedback signal.

Claim 4

The phase locked loop circuit as claimed in claim 3, characterized in that said memory means (7, 8) includes an analog-to-digital converter (7) for converting an output signal of said lowpass filter (4) into a digital signal, and a memory (8) which receives the digital signal from said analog-to-digital converter.

Claim 5

The phase locked loop circuit as claimed in claim 4, which further comprises control means (50), coupled to said dividing means (10) and said memory means (7, 8), for controlling a frequency dividing ratio of said dividing means and for controlling read and write operations and a storage location of said memory means.

Claim 6

The phase locked loop circuit as claimed in any of claims 1 to 5, characterized in that said phase comparator means (2, 3) successively receives the input signal of each of a plurality of channels.

Claim 7

The phase locked loop circuit as claimed in any of claims 1 to 6, characterized in that there are further provided a crystal oscillator (1a) for generating an oscillation signal, and counter means (1) for generating the input signal based on the oscillation signal.

Claim 8

The phase locked loop circuit as claimed in any of claims 1 to 7, characterized in that said memory means (7, 8) stores the information related to the input signal when the power source is turned ON, and said control voltage output means (15) outputs the control voltage based on the information read out from said memory means after a predetermined time elapses from a time when the power source is turned ON.

Claim 9

A phase locked loop circuit comprising phase comparator means (2, 3) for comparing phases of an input signal and a feedback signal and for outputting an output signal dependent on a phase error between the two compared signals; lowpass filter means (4), coupled to said phase comparator means, for filtering the output signal of said phase comparator means into a control signal; and a feedback loop circuit (5, 10) including a voltage controlled oscillator (5) which is coupled to said lowpass filter means, said voltage controlled oscillator oscillating at an oscillation frequency controlled by the control signal received from said lowpass filter means, said feedback loop circuit supplying a signal which is derived from an output signal of said voltage controlled oscillator to said phase comparator means as the feedback signal, characterized in that there are provided: switching means (6, 61, 62), coupled to said lowpass filter means (4), having first and second states; an analog-to-digital converter (7), coupled to said switching means, for converting the control signal which is received from said lowpass filter means via said switching means in the first state into a digital signal; memory means (8), coupled to said analog-to-digital converter, for storing the digital signal output from said analog-to-digital converter; and a digital-to-analog converter (9), coupled to said memory means and said switching means, for converting the digital signal read out from said memory means into an analog signal and for supplying the analog signal to said switching means; said switching means in the second state supplying the analog signal from said digital-to-analog converter to one of said lowpass filter means and said voltage controlled oscillator.

Claim 10

The phase locked loop circuit as claimed in claim 9, characterized in that at least said phase comparator means (2, 3), said switching means (6, 61, 62), said analog-to-digital converter (7), said memory means (8) and said digital-to-analog converter (9) are formed on a single semiconductor integrated circuit chip.

Claim 11

The phase locked loop circuit as claimed in claim 9 or 10 which is operatively coupled to a power source, characterized in that said switching means (6, 61, 62) takes the first state when the power source turns ON and takes the second state after a predetermined time elapses from a time when the power source turns ON.

Claim 12

The phase locked loop circuit as claimed in any of claims 9 to 11, characterized in that said switching means (6, 61, 62) includes a switch (6) which is coupled between an output of said digital-to-analog converter (9) and an input of said lowpass filter means (4), and a line which couples an output of said lowpass filter means to an input of said analog-to-digital converter (7), said switch being open in the first state of said switching means and being closed in the second state of said switching means.

Claim 13

The phase locked loop circuit as claimed in any of claims 9 to 12, characterized in that said feedback loop circuit (5, 10) includes a dividing circuit (10) which is coupled between said voltage controlled oscillator (5) and said phase comparator means (2, 3) for frequency-dividing the output oscillation frequency of said voltage controlled oscillator and for outputting the feedback signal.

Claim 14

The phase locked loop circuit as claimed in claim 13, characterized in that there are further provided first means (12) for generating in response to a program signal a first control signal which controls a frequency-dividing ratio of said dividing circuit (10) and a second control signal, and second means (12) coupled to said memory means (8) for specifying a storage location within said memory means in response to the second control signal.

Claim 15

The phase locked loop circuit as claimed in any of claims 9, 10, 11, 13 and 14, characterized in that said switching means (6, 61, 62) includes a first switch (61) which is coupled between an output of said lowpass filter means (4) and an input of said analog-to-digital converter (7), said first switch being closed in the first state of said switching means and open in the second state of said switching means, and a second switch (62) which couples an output of said phase comparator means (2, 3) to an input of said lowpass filter means in the first state of said switching means and couples an output of said digital-to-analog converter (9) to the input of said lowpass filter means in the second state of said switching means.

Claim 16

The phase locked loop circuit as claimed in claim 15, characterized in that said first switch (61) is closed in response to a first signal and said second switch (62) couples the output of said digital-to-analog converter (9) to the input of said lowpass filter means (4) in response to a second signal.

Claim 17

The phase locked loop circuit as claimed in claim 16, characterized in that there are further provided first means (11) for generating in response to a program signal a first control signal which controls a frequency-dividing ratio of said dividing circuit (10) and a second control signal, and second means (12) coupled to said memory means (8) for specifying a storage location within said memory means in response to the second control signal, said second means making a write operation with respect to said memory means in response to the first signal and making a read operation with respect to said memory means in response to the second signal.

Claim 18

The phase locked loop circuit as claimed in any of claims 9 to 17, characterized in that there is further provided initial phase matching means (13a, 13), coupled to said voltage controlled oscillator (5), for generating an initial phase signal based on the input signal and the output signal of said voltage controlled oscillator during an initial operation in which a target frequency is set, said initial phase signal being supplied to said phase comparator (2, 3) so that an initial phase matching of the input signal and the feedback signal is made therein.

Claim 19

The phase locked loop circuit as claimed in any of claims 9 to 18, characterized in that said phase comparator means (2, 3) successively receives the input signal of each of a plurality of channels.

Claim 20

The phase locked loop circuit as claimed in any of claims 9 to 19, characterized in that there are further provided a crystal oscillator (1a) for generating an oscillation signal, and counter means (1) for generating the input signal based on the oscillation signal.